ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 28

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
AVGAIN, BVGAIN, and CVGAIN registers are accessed as
32-bit registers with four MSBs padded with 0s and sign
extended to 28 bits.
Voltage Channel HPF
As explained in the Current Channel HPF section, the ADC
outputs can contain a dc offset that can create errors in power
and rms calculations. HPFs are placed in the signal path of the
phase voltages, similar to the ones in the current channels. The
bit 0 (HPFEN) of CONFIG3 register can enable or disable the
filters. See the Current Channel HPF section for more details.
Voltage Channel Sampling
The waveform samples of the voltage channel are taken at the
output of HPF and stored into VAWV, VBWV, and VCWV
24-bit signed registers at a rate of 8 kSPS. All power and rms
calculations remain uninterrupted during this process. Bit 17
(DREADY) in the STATUS0 register is set when the VAWV,
VBWV, and VCWV registers are available to be read using the
I
register enables an interrupt to be set when the DREADY flag is
set. See the Digital Signal Processor section for more details on
Bit DREADY.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to registers presented in Figure 19, the VAWV, VBWV,
and VCWV 24-bit signed registers are transmitted sign
extended to 32 bits.
The ADE7880 contains an HSDC port especially designed to
provide fast access to the waveform sample registers. See the
HSDC Interface section for more details.
CHANGING PHASE VOLTAGE DATAPATH
The ADE7880 can direct one phase voltage input to the
computational datapath of another phase. For example, Phase A
voltage can be introduced in the Phase B computational datapath,
which means all powers computed by the ADE7880 in Phase B
are based on Phase A voltage and Phase B current.
Bits[9:8] (VTOIA[1:0]) of the CONFIG register manage the
Phase A voltage measured at the VA pin. If VTOIA[1:0] = 00
(default value), the voltage is directed to the Phase A computa-
tional datapath. If VTOIA[1:0] = 01, the voltage is directed to
the Phase B path. If VTOIA[1:0] = 10, the voltage is directed to the
Phase C path. If VTOIA[1:0] = 11, the ADE7880 behaves as if
VTOIA[1:0] = 00.
Bits[11:10] (VTOIB[1:0]) of the CONFIG register manage the
Phase B voltage measured at the VB pin. If VTOIB[1:0] = 00
(default value), the voltage is directed to the Phase B computa-
tional datapath. If VTOIB[1:0] = 01, the voltage is directed to
the Phase C path. If VTOIB[1:0] = 10, the voltage is directed to
2
C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0
Rev. PrE | Page 28 of 103
the Phase A path. If VTOIB[1:0] = 11, the ADE7880 behaves
as if VTOIB[1:0] = 00.
Bits[13:12] (VTOIC[1:0]) of the CONFIG register manage the
Phase C voltage measured at the VC pin. If VTOIC[1:0] = 00
(default value), the voltage is directed to Phase C computational
datapath, if VTOIC[1:0] = 01, the voltage is directed to the
Phase A path. If VTOIC[1:0] = 10, the voltage is directed to the
Phase B path. If VTOIC[1:0] = 11, the ADE7880 behaves as if
VTOIC[1:0] = 00.
Figure 24 presents the case in which Phase A voltage is used in
the Phase B datapath, Phase B voltage is used in the Phase C
datapath, and Phase C voltage is used in the Phase A datapath.
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
The ADE7880 has a zero-crossing (ZX) detection circuit on the
phase current and voltage channels. The neutral current
datapath does not contain a zero-crossing detection circuit.
Zero-crossing events are used as a time base for various power
quality measurements and in the calibration process.
The output of LPF1 is used to generate zero crossing events.
The low-pass filter is intended to eliminate all harmonics of
50 Hz and 60 Hz systems, and to help identify the zero-crossing
events on the fundamental components of both current and
voltage channels.
The digital filter has a pole at 80 Hz and is clocked at 256 kHz.
As a result, there is a phase lag between the analog input signal
(one of IA, IB, IC, VA, VB, and VC) and the output of LPF1.
The error in ZX detection is 0.0703° for 50 Hz systems (0.0843°
for 60 Hz systems). The phase lag response of LPF1 results in a
time delay of approximately 31.4° or 1.74 ms (at 50 Hz) between
its input and output. The overall delay between the zero crossing
on the analog inputs and ZX detection obtained after LPF1 is
about 39.6° or 2.2 ms (at 50 Hz). The ADC and HPF introduce
the additional delay. The LPF1 cannot be disabled to assure a
VA
VB
VC
IA
IB
IC
Figure 24. Phase Voltages Used in Different Datapaths
APHCAL
BPHCAL
CPHCAL
Preliminary Technical Data
COMPUTATIONAL
COMPUTATIONAL
COMPUTATIONAL
DATAPATH
DATAPATH
DATAPATH
PHASE A
PHASE B
PHASE C
PHASE A VOLTAGE
PHASE B VOLTAGE
PHASE C VOLTAGE
VTOIA[1:0] = 01,
VTOIB[1:0] = 01,
VTOIC[1:0] = 01,
TO PHASE B
TO PHASE C
TO PHASE A
DIRECTED
DIRECTED
DIRECTED