ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 69

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
The following bits in the MASK1 register work with the status bits
in the IPEAK and VPEAK registers, respectively:
•
•
The following bits in the MASK0 register work with the status bits
in the PHSIGN register:
•
•
•
When the STATUSx register is read and one of these bits is set
to 1, the status register associated with the bit is immediately
read to identify the phase that triggered the interrupt and only
at that time can the STATUSx register be written back with the bit
set to 1.
Using the Interrupts with an MCU
Figure 73 shows a timing diagram that illustrates a suggested
implementation of the ADE7880 interrupt management using an
MCU. At Time t
one or more interrupt events have occurred in the ADE7880, at
which point the following steps should be taken:
1.
2.
status register is read immediately to identify the phase that
triggered the interrupt. The name, PHx, in Figure 74 denotes
one of the PHSTATUS, IPEAK, VPEAK, or PHSIGN registers.
Then, STATUSx is written back to clear the status flag(s).
SERIAL INTERFACES
The ADE7880 has three serial port interfaces: one fully licensed
I
speed data capture port (HSDC). As the SPI pins are
multiplexed with some of the pins of the I
SEQUENCE
2
PROGRAM
C interface, one serial peripheral interface (SPI), and one high
Bit 23 (PKI)
Bit 24 (PKV)
Bits[6:8] (REVAPx)
Bits[10:12] (REVRPx)
Bit 9, Bit 13, and Bit 18 (REVPSUMx)
Tie the
interrupt on the MCU.
On detection of the negative edge, configure the MCU to
start executing its interrupt service routine (ISR).
IRQx
SEQUENCE
PROGRAM
IRQx
t
IRQx
1
TO ISR
JUMP
1
, the IRQx
pin to a negative-edge-triggered external
t
1
INTERRUPT
TO ISR
JUMP
GLOBAL
MASK
Figure 74. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved
pin goes active low indicating that
INTERRUPT
GLOBAL
MASK
CLEAR MCU
INTERRUPT
FLAG
CLEAR MCU
INTERRUPT
2
FLAG
C and HSDC ports,
STATUSx
READ
STATUSx
READ
STATUSx
WRITE
BACK
Figure 73. Interrupt Management
t
2
Rev. PrE | Page 69 of 103
READ
PHx
(BASED ON STATUSx CONTENTS)
STATUSx
WRITE
ISR ACTION
BACK
3.
4.
5.
If a subsequent interrupt event occurs during the ISR (t
event is recorded by the MCU external interrupt flag being set
again.
On returning from the ISR, the global interrupt mask bit is
cleared (same instruction cycle) and the external interrupt flag
uses the MCU to jump to its ISR once again. This ensures that
the MCU does not miss any external interrupts.
Figure 74 shows a recommended timing diagram when the
status bits in the STATUSx registers work in conjunction with
bits in other registers. When the IRQx pin goes active low, the
STATUSx register is read, and if one of these bits is 1, a second
the ADE7880 accepts two configurations: one using the SPI
port only and one using the I
HSDC port.
Serial Interface Choice
After reset, the HSDC port is always disabled. Choose between
the I
power-up or after a hardware reset. If the SS/HSA pin is kept
high, then the ADE7880 uses the I
reset is executed. If the SS
t
2
t
3
(BASED ON STATUSx CONTENTS)
2
On entering the ISR, disable all interrupts using the global
interrupt mask bit. At this point, the MCU external
interrupt flag can be cleared to capture interrupt events
that occur during the current ISR.
When the MCU interrupt flag is cleared, a read from
STATUSx, the interrupt status register, is carried out. The
interrupt status register content is used to determine the
source of the interrupt(s) and, hence, the appropriate
action to be taken.
The same STATUSx content is written back into the
ADE7880 to clear the status flag(s) and reset the IRQx
to logic high (t
C and SPI ports by manipulating the SS/has pin after
ISR ACTION
MCU
INTERRUPT
FLAG SET
GLOBAL INTERRUPT
MASK RESET
ISR RETURN
t
2
3
).
/HSA pin is toggled high to low three
MCU
INTERRUPT
FLAG SET
2
C port in conjunction with the
GLOBAL INTERRUPT
TO ISR
JUMP
MASK RESET
ISR RETURN
2
C port until a new hardware
TO ISR
JUMP
ADE7880
3
), that
line