ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 92

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
Table 36. MASK1 Register (Address 0xE50B)
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22:21
23
24
25
Bit Mnemonic
NLOAD
FNLOAD
VANLOAD
ZXTOVA
ZXTOVB
ZXTOVC
ZXTOIA
ZXTOIB
ZXTOIC
ZXVA
ZXVB
ZXVC
ZXIA
ZXIB
ZXIC
RSTDONE
SAG
OI
OV
SEQERR
MISMTCH
Reserved
PKI
PKV
CRC
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
0
Description
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition determined by the total active power and VNOM based apparent power.
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on fundamental active and reactive powers.
When this bit is set to 1, it enables an interrupt when at least one phase enters no load
condition based on apparent power.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A current is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B current is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C current is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
current.
Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality
attached. It can be set to 1 or cleared to 0 without having any effect.
When this bit is set to 1, it enables an interrupt when one of the phase voltages entered or
exited a sag state. The phase is indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS
register (see Table 37).
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of
the phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 37).
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of
the phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 37).
When this bit is set to 1, it enables an interrupt when a negative-to-positive zero crossing on
Phase A voltage is not followed by a negative-to-positive zero crossing on Phase B voltage,
but by a negative-to-positive zero crossing on Phase C voltage.
When this bit is set to 1, it enables an interrupt when
greater than the value indicated in ISUMLVL register.
Reserved. These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the current channel has ended.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the voltage channel has ended.
When this bit is set to 1, it enables an interrupt when the latest CHECKSUM value is different
from the CHECKSUM value computed when RUN register was set to 1.
Rev. PrE| Page 92 of 103
Preliminary Technical Data
ISUM
−
INWV
>
ISUMLVL
is