ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 23

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
THEORY OF OPERATION
ANALOG INPUTS
The ADE7880 has seven analog inputs forming current and
voltage channels. The current channels consist of four pairs of
fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP
and ICN, and INP and INN. These voltage input pairs have a
maximum differential signal of ±0.5 V.
The maximum signal level on analog inputs for the IxP/IxN
pair is also ±0.5 V with respect to AGND. The maximum
common-mode signal allowed on the inputs is ±25 mV. Figure 10
presents a schematic of the input for the current channels and
their relation to the maximum common-mode voltage.
All inputs have a programmable gain amplifier (PGA) with a
possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and
IC inputs is set in Bits[2:0] (PGA1[2:0]) of the gain register. The
gain of the IN input is set in Bits[5:3] (PGA2[2:0]) of the gain
register; thus, a different gain from the IA, IB, or IC inputs is
possible. See Table 40 for details on the gain register.
The voltage channel has three single-ended voltage inputs: VAP,
VBP, and VCP. These single-ended voltage inputs have a maximum
input voltage of ±0.5 V with respect to VN. The maximum
signal level on analog inputs for VxP and VN is also ±0.5 V
with respect to AGND. The maximum common-mode signal
allowed on the inputs is ±25 mV. Figure 11 presents a schematic
of the voltage channels inputs and their relation to the maximum
common-mode voltage.
All inputs have a programmable gain with a possible gain
selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]
(PGA3[2:0]) in the gain register (see Table 40).
Figure 12 shows how the gain selection from the gain register
works in both current and voltage channels.
+500mV
–500mV
Figure 11. Maximum Input Level, Voltage Channels, Gain = 1
Figure 10. Maximum Input Level, Current Channels, Gain = 1
V
CM
V
+500mV
–500mV
1
+ V
V
CM
2
V
1
V
1
DIFFERENTIAL INPUT
+ V
V
V
1
V
COMMON MODE
2
CM
CM
DIFFERENTIAL INPUT
+ V
= 500mV MAX PEAK
V
= ±25mV MAX
COMMON MODE
2
CM
= 500mV MAX PEAK
V
V
= ±25mV MAX
1
CM
V
V
1
2
VAP, VBP,
OR VCP
ICN, OR INN
VN
ICP, OR INP
IAP, IBP,
IAN, IBN,
Rev. PrE | Page 23 of 103
ANALOG-TO-DIGITAL CONVERSION
The ADE7880 has seven sigma-delta (Σ-Δ) analog-to-digital
converters (ADCs). In PSM0 mode, all ADCs are active. In
PSM1 mode, only the ADCs that measure the Phase A, Phase B,
and Phase C currents are active. The ADCs that measure the
neutral current and the A, B, and C phase voltages are turned
off. In PSM2 and PSM3 modes, the ADCs are powered down to
minimize power consumption.
For simplicity, the block diagram in Figure 13 shows a first-
order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator
and the digital low-pass filter.
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7880, the sampling clock is equal to 1.024 MHz
(CLKIN/16). The 1-bit DAC in the feedback loop is driven by
the serial data stream. The DAC output is subtracted from the
input signal. If the loop gain is high enough, the average value
of the DAC output (and, therefore, the bit stream) can approach
that of the input signal level. For any given input value in a
single sampling interval, the data from the 1-bit ADC is
virtually meaningless. Only when a large number of samples are
averaged is a meaningful result obtained. This averaging is
carried out in the second part of the ADC, the digital low-pass
filter. By averaging a large number of bits from the modulator,
the low-pass filter can produce 24-bit data-words that are
proportional to the input signal level.
The Σ-Δ converter uses two techniques to achieve high resolu-
tion from what is essentially a 1-bit conversion technique. The
first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency) that is many times higher than
the bandwidth of interest. For example, the sampling rate in
the ADE7880 is 1.024 MHz, and the bandwidth of interest is
LOW-PASS FILTER
ANALOG
R
C
Figure 12. PGA in Current and Voltage Channels
IxP, VyP
IxN, VN
NOTES
1. x = A, B, C, N
+
y = A, B, C.
Figure 13. First-Order
–
INTEGRATOR
V
IN
V
REF
1-BIT DAC
CLKIN/16
.....10100101.....
K × V
+
–
GAIN
SELECTION
LATCHED
COMPARATOR
IN
Σ
-∆ ADC
ADE7880
LOW-PASS
DIGITAL
FILTER
24