ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 74

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
to-low transition of SCLK. The SPI of the ADE7880 samples
data on the low-to-high transitions of SCLK. Next, the master
sends the 16-bit address of the first harmonic calculations
register that is read. After the ADE7880 receives the last bit of
the address of the register on a low-to-high transition of SCLK,
it begins to transmit its contents on the MISO line when the
next SCLK high-to-low transition occurs; thus, the master can
sample the data on a low-to-high SCLK transition. After the
master receives the last bit of the first register, the ADE7880
sends the harmonic calculations register placed at the next
location and so forth until the master sets the SS
lines high and the communication ends. The data lines, MOSI
and MISO, go into a high impedance state. See Figure 80 for
details of the SPI read operation of harmonic calculations
registers.
SPI Write Operation
HSDC Interface
The high speed data capture (HSDC) interface is disabled after
default. It can be used only if the ADE7880 is configured with an
I
the same time with HSDC.
Bit 6 (HSDCEN) in the CONFIG register activates HSDC when
set to 1. If Bit HSDCEN is cleared to 0, the default value, the
HSDC interface is disabled. Setting Bit HSDCEN to 1 when SPI
is in use does not have any effect. HSDC is an interface for
sending to an external device (usually a microprocessor or a
DSP) up to sixteen 32-bit words. The words represent the
instantaneous values of the phase currents and voltages, neutral
current, and active, reactive, and apparent powers. The registers
being transmitted include IAWV, VAWV, IBWV, VBWV, ICWV,
VCWV, AVA, INWV, BVA, CVA, AWATT, BWATT, CWATT,
AFVAR, BFVAR, and CFVAR. All are 24-bit registers that are
sign extended to 32-bits (see Figure 19 for details).
HSDC can be interfaced with SPI or similar interfaces. HSDC is
always a master of the communication and consists of three
pins: HSA, HSD, and HSCLK. HSA represents the select signal.
It stays active low or high when a word is transmitted and it is
usually connected to the select pin of the slave. HSD sends data
2
C interface. The SPI interface of ADE7880 cannot be used in
SCLK
MOSI
SS
0
0
Figure 81. SPI Write Operation of a 32-Bit Register
and SCLK
0
0
0 0 0 0
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15 14
REGISTER ADDRESS
The write operation using the SPI interface of the ADE7880
initiates when the master sets the SS/HSA pin low and begins
sending one byte representing the address of the ADE7880 on
the MOSI line. The master sets data on the MOSI line starting
with the first high-to-low transition of SCLK. The SPI of the
ADE7880 samples data on the low-to-high transitions of SCLK.
The most significant seven bits of the address byte can have any
value, but as a good programming practice, they should be
different from 0111000b, the seven bits used in the I
Bit 0 (read/write) of the address byte must be 0 for a write
operation. Next, the master sends both the 16-bit address of the
register that is written and the 32-, 16-, or 8-bit value of that
register without losing any SCLK cycle. After the last bit is
transmitted, the master sets the SS and SCLK lines high at the
end of the SCLK cycle and the communication ends. The data
lines, MOSI and MISO, go into a high impedance state. See
Figure 81 for details of the SPI write operation.
to the slave and it is usually connected to the data input pin of
the slave. HSCLK is the serial clock line that is generated by the
ADE7880 and it is usually connected to the serial clock input of
the slave. Figure 82 shows the connections between the
ADE7880 HSDC and slave devices containing an SPI interface.
The HSDC communication is managed by the HSDC_CFG
register (see Table 49). It is recommended to set the HSDC_CFG
register to the desired value before enabling the port using Bit 6
(HSDCEN) in the CONFIG register. In this way, the state of
various pins belonging to the HSDC port do not take levels incon-
sistent with the desired HSDC behavior. After a hardware reset
or after power-up, the MISO/HSD and SS/HSA pins are set high.
1 0 31 30
REGISTER VALUE
ADE7880
Figure 82. Connecting the ADE7880 HSDC with an SPI
HSCLK
Preliminary Technical Data
1 0
HSD
HSA
MISO
SCK
SS
device
SPI
2
C protocol.