ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 31

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Period Measurement
The ADE7880 provides the period measurement of the line in
the voltage channel. The period of each phase voltage is
measured and stored in three different registers, APERIOD,
BPERIOD, and CPERIOD. The period registers are 16-bit
unsigned registers and update every line period. Because of the
LPF1 filter (see Figure 25), a settling time of 30 ms to 40 ms is
associated with this filter before the measurement is stable.
The period measurement has a resolution of 3.90625 μs/LSB
(256 kHz clock), which represents 0.0195% (50 Hz/256 kHz)
when the line frequency is 50 Hz and 0.0234% (60 Hz/256 kHz)
when the line frequency is 60 Hz. The value of the period registers
for 50 Hz networks is approximately 5120 (256 kHz/50 Hz) and
for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The
length of the registers enables the measurement of line
frequencies as low as 3.9 Hz (256 kHz/2
are stable at ±1 LSB when the line is established and the
measurement does not change.
The following expressions can be used to compute the line
period and frequency using the period registers:
Phase Voltage Sag Detection
The ADE7880 can be programmed to detect when the absolute
value of any phase voltage drops below or grows above a certain
peak value for a number of half-line cycles. The phase where
this event takes place and the state of the phase voltage relative
to the threshold is identified in Bits[14:12] (VSPHASE[x]) of
the PHSTATUS register. An associated interrupt is triggered
when any phase drops below or grows above a threshold. This
condition is illustrated in Figure 31.
Figure 31 shows Phase A voltage falling below a threshold that
is set in the SAG level register (SAGLVL) for four half-line
cycles (SAGCYC = 4). When Bit 16 (SAG) in the STATUS1 register
is set to 1 to indicate the condition, Bit VSPHASE[0] in the
PHSTATUS register is also set to 1 because the phase A voltage is
below SAGLVL. The microcontroller then writes back STATUS1
register with Bit 16 (SAG) set to 1 to erase the bit and bring IRQ1
interrupt pin back high. Then the phase A voltage stays above the
SAGLVL threshold for four half-line cycles (SAGCYC=4). The Bit
16 (SAG) in STATUS1 register is set to 1 to indicate the condition
and the bit VSPHASE[0] in the PHSTATUS register is set back to 0.
Bits VSPHASE[1] and VSPHASE[2] relate to the sag events on
phases B and C in the same way: when phase B or phase C
voltage stays below SAGLVL, they are set to 1. When the phase
voltages are above SAGLVL, they are set to 0.
T
f
L
L
=
=
PERIOD[15:
PERIOD[15:
256
256
3 E
3 E
0]
0]
[ ]
[
sec
Hz
]
16
). The period registers
Rev. PrE | Page 31 of 103
(6)
(7)
The SAGCYC register represents the number of half-line cycles
the phase voltage must remain below or above the level
indicated in the SAGLVL register to trigger a SAG interrupt ; 0
is not a valid number for SAGCYC. For example, when the SAG
cycle (SAGCYC[7:0]) contains 0x07, the SAG flag in the STATUS1
register is set at the end of the seventh half line cycle for which
the line voltage falls below the threshold. If Bit 16 (SAG) in
MASK1 is set, the IRQ1 interrupt pin is driven low in case of a
SAG event in the same moment the Status Bit 16 (SAG) in
STATUS1 register is set to 1. The SAG status bit in the STATUS1
register aand the
STATUS1 register with the status bit set to 1.
Back to
indicated threshold into the SAGLVL register for two line
cycles, Bit VSPHASE[1] in the PHSTATUS register is set to 1.
Simultaneously, Bit 16 (SAG) in the STATUS1 register is set to 1 to
indicate the condition.
Note that the internal zero-crossing counter is always active. By
setting the SAGLVL register, the first SAG detection result is,
therefore, not executed across a full SAGCYC period. Writing to
the SAGCYC register when the SAGLVL register is already initia-
lized resets the zero-crossing counter, thus ensuring that the first
SAG detection result is obtained across a full SAGCYC period.
The recommended procedure to manage SAG events is the
following:
STATUS1[31:0]
PHSTATUS[12]
PHSTATUS[13]
Bit 16 (SAG) in
SAGLVL[23:0]
SAGLVL[23:0]
VSPHASE[0]=
VSPHASE[1]=
FULL SCALE
FULL SCALE
IRQ1\ pin
SAGCYC[7:0]=0x4
Figure 31: when the Phase B voltage falls below the
IRQ1 pin is returned to high by writing to the
PHASE B VOLTAGE
SAGCYC[7:0]=0x4
PHASE A VOLTAGE
Figure 31. SAG Detection
STATUS1[16] cancelled by
a write to STATUS1[31:0]
with SAG bit set
STATUS[16] set to 1
IRQ1\ pin goes high
because STATUS1[16]
cancelled by a write to
STATUS[31:0] with SAG
bit set
PHSTATUS[12] set to 1
because phase A voltage
was below SAGLVL for
SAGCYC half line cycles
PHSTATUS[12] cleared to
0 because phase A
voltage was above
SAGLVL for SAGCYC half
line cycles
PHSTATUS[13] set to 1
ADE7880