ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 96

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
Bit
Location
11
12
13
14
15
Table 42. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bit
Location
9:0
15:10
Table 43. PHSIGN Register (Address 0xE617)
Bit
Location
0
1
2
3
4
5
6
7
8
Bit Mnemonic
CF3DIS
CF1LATCH
CF2LATCH
CF3LATCH
Reserved
Bit Mnemonic
PHCALVAL
Reserved
Bit Mnemonic
AWSIGN
BWSIGN
CWSIGN
SUM1SIGN
AFVARSIGN
BFVARSIGN
CFVARSIGN
SUM2SIGN
SUM3SIGN
Default Value
1
0
0
0
0
Default Value
0000000000
000000
Default Value
0
0
0
0
0
0
0
0
0
Description
When this bit is set to 1, the CF3 output is disabled. The respective digital to frequency
converter remains enabled even if CF3DIS = 1.
When this bit is set to 0, the CF3 output is enabled.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF1 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF2 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF3 pulse is generated. See the Synchronizing Energy Registers with CFx Outputs section.
Reserved. This bit does not manage any functionality.
Description
If current channel compensation is necessary, these bits can vary only between 0 and 383.
If voltage channel compensation is necessary, these bits can vary only between 512 and 575.
If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves
like PHCALVAL set between 256 and 383.
If the PHCALVAL bits are set with numbers between 576 and 1023, the compensation
behaves like PHCALVAL bits set between 384 and 511.
Reserved. These bits do not manage any functionality.
Description
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive.
1: if the active power identified by Bit 6 (REVAPSEL) bit in the ACCMODE register (total of
fundamental) on Phase C is negative.
0: if the sum of all phase powers in the CF1 datapath is positive.
1: if the sum of all phase powers in the CF1 datapath is negative. Phase powers in the CF1
datapath are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[x]) of the CFMODE register.
0: if the fundamental reactive power on Phase A is positive.
1: if the fundamental reactive power on Phase A is negative.
0: if the fundamental reactive power on Phase B is positive.
1: if the fundamental reactive power on Phase B is negative.
0: if the fundamental reactive power on Phase C is positive.
1: if the fundamental reactive power on Phase C is negative.
0: if the sum of all phase powers in the CF2 datapath is positive.
1: if the sum of all phase powers in the CF2 datapath is negative. Phase powers in the CF2
datapath are identified by Bits[5:3] (TERMSEL2[x]) of the COMPMODE register and by
Bits[5:3] (CF2SEL[x]) of the CFMODE register.
0: if the sum of all phase powers in the CF3 datapath is positive.
Rev. PrE| Page 96 of 103
Preliminary Technical Data