ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 85

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Address
0xE60B
0xE60C
0xE60D
0xE60E
0xE60F
0xE610
0xE611
0xE612
0xE613
0xE614
0xE615
0xE616
0xE617
0xE618
0xE700
0xE701
0xE702
0xE703
0xE704
0xE705
0xE706
0xE707
0xE7FD
Register Name
LINECYC
ZXTOUT
COMPMODE
Gain
CFMODE
CF1DEN
CF2DEN
CF3DEN
APHCAL
BPHCAL
CPHCAL
PHSIGN
CONFIG
MMODE
ACCMODE
LCYCMODE
PEAKCYC
SAGCYC
CFCYC
HSDC_CFG
Version
LAST_RWDATA8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
1
Bit
Length
16
16
16
16
16
16
16
16
10
10
10
16
16
8
8
8
8
8
8
8
8
8
Bit Length
During
Communication
16
16
16
16
16
16
16
16
16 ZP
16 ZP
16 ZP
16
16
8
8
8
8
8
8
8
8
8
Rev. PrE | Page 85 of 103
2
Type
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
3
Default
Value
0xFFFF
0xFFFF
0x01FF
0x0000
0x0EA0
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
0x0002
0x1C
0x80
0x78
0x00
0x00
0x01
0x00
N/A
4
Description
written for proper operation.
Line cycle accumulation mode
count.
Zero-crossing timeout count.
Computation-mode register. See
Table 39.
PGA gains at ADC inputs. See Table
40.
CFx configuration register. See Table
41.
CF1 denominator.
CF2 denominator.
CF3 denominator.
Phase calibration of Phase A. See
Table 42.
Phase calibration of Phase B. See
Table 42.
Phase calibration Phase of C. See
Table 42.
Power sign register. See Table 43.
ADE7880 configuration register.
See Table 44.
Measurement mode register.
See Table 45.
Accumulation mode register.
See Table 46.
Line accumulation mode behavior.
See Table 48.
Peak detection half line cycles.
SAG detection half line cycles.
Number of CF pulses between two
consecutive energy latches. See the
Synchronizing Energy Registers
with CFx Outputs section.
HSDC configuration register. See
Table 49.
Version of die.
Contains the data from the last
successful 8 bit register
communication.
ADE7880