ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 75

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bit 0 (HCLK) in the HSDC_CFG register determines the serial
clock frequency of the HSDC communication. When HCLK is
0 (the default value), the clock frequency is 8 MHz. When HCLK
is 1, the clock frequency is 4 MHz. A bit of data is transmitted
for every HSCLK high-to-low transition. The slave device that
receives data from HSDC samples the HSD line on the low-to-
high transition of HSCLK.
The words can be transmitted as 32-bit packages or as 8-bit
packages. When Bit 1 (HSIZE) in the HSDC_CFG register is 0 (the
default value), the words are transmitted as 32-bit packages. When
Bit HSIZE is 1, the registers are transmitted as 8-bit packages. The
HSDC interface transmits the words MSB first.
Bit 2 (HGAP) introduces a gap of seven HSCLK cycles between
packages when Bit 2 (HGAP) is set to 1. When Bit HGAP is
cleared to 0 (the default value), no gap is introduced between
packages and the communication time is shortest. In this case,
HSIZE does not have any influence on the communication and
a data bit is placed on the HSD line with every HSCLK high-to-
low transition.
Bits[4:3] (HXFER[1:0]) decide how many words are transmitted.
When HXFER[1:0] is 00, the default value, then all 16 words are
transmitted. When HXFER[1:0] is 01, only the words representing
the instantaneous values of phase and neutral currents and phase
voltages are transmitted in the following order: IAWV, VAWV,
IBWV, VBWV, ICWV, VCWV, and one 32-bit word that is always
equal to INWV. When HXFER[1:0] is 10, only the instantaneous
values of phase powers are transmitted in the following order:
AVA, BVA, CVA, AWATT, BWATT, CWATT, AFVAR, BFVAR,
and CFVAR. The value, 11, for HXFER[1:0] is reserved and
writing it is equivalent to writing 00, the default value.
Bit 5 (HSAPOL) determines the polarity of HSA function of the
SS/HSA pin during communication. When HSAPOL is 0 (the
default value), HSA is active low during the communication.
This means that HSA stays high when no communication is in
Table 24. Communication Times for Various HSDC Settings
HXFER[1:0]
00
00
00
00
00
00
01
01
01
01
01
01
10
10
HGAP
0
0
1
1
1
1
0
0
1
1
1
1
0
0
HSIZE
N/A
N/A
0
0
1
1
N/A
N/A
0
0
1
1
N/A
N/A
1
Rev. PrE | Page 75 of 103
HCLK
0
1
0
1
0
1
0
1
0
1
0
1
0
1
progress. When the communication starts, HSA goes low and
stays low until the communication ends. Then it goes back to
high. When HSAPOL is 1, the HSA function of the SS
is active high duringthe communication. This means that HSA
stays low when no communication is in progress. When the
communication starts, HSA goes high and stays high until the
communication ends; then, it goes back to low.
Bits[7:6] of the HSDC_CFG register are reserved. Any value
written into these bits does not have any consequence on HSDC
behavior.
Figure 83 shows the HSDC transfer protocol for HGAP = 0,
HXFER[1:0] = 00 and HSAPOL = 0. Note that the HSDC
interface sets a data bit on the HSD line every HSCLK high-to-
low transition and the value of Bit HSIZE is irrelevant.
Figure 84 shows the HSDC transfer protocol for HSIZE = 0,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 32-bit word.
Figure 85 shows the HSDC transfer protocol for HSIZE = 1,
HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the
HSDC interface introduces a seven-HSCLK cycles gap between
every 8-bit word.
See Table 49 for the HSDC_CFG register and descriptions for
the HCLK, HSIZE, HGAP, HXFER[1:0], and HSAPOL bits.
Table 24 lists the time it takes to execute an HSDC data transfer
for all HSDC_CFG register settings. For some settings, the
transfer time is less than 125 μs (8 kHz), the waveform sample
registers update rate. This means the HSDC port transmits data
every sampling cycle. For settings in which the transfer time is
greater than 125 μs, the HSDC port transmits data only in the
first of two consecutive 8 kHz sampling cycles. This means it
transmits registers at an effective rate of 4 kHz.
Communication Time (µs)
64
128
77.125
154.25
119.25
238.25
28
56
33.25
66.5
51.625
103.25
36
72
ADE7880
/HSA pin