ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 71

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
I
The read operation using the I
accomplished in two stages. The first stage sets the pointer to
the address of the register. The second stage reads the content of
the register.
As seen in Figure 76, the first stage initiates when the master
generates a start condition and consists in one byte representing
the address of the ADE7880 followed by the 16-bit address of the
target register. The ADE7880 acknowledges every byte received.
The address byte is similar to the address byte of a write
operation and is equal to 0x70 (see the I
section for details). After the last byte of the register address has
been sent and acknowledged by the ADE7880, the second stage
2
S
T
A
R
T
S 0 1 1 1 0 0 0
C Read Operation
slave address
S
A
R
S 0 1 1 1 0 0 0
S
A
R
S
T
T
T
T
0 1 1 1 0 0 0
slave address
slave address
0
A
C
K
15
MS 8 bits of reg
ACK generated by
address
2
ADE7880
C interface of the ADE7880 is
0
1
A
C
K
A
C
K
15
31
8
A
C
K
Byte3 (MS) of reg
2
MS 8 bits of reg
C Write Operation
7
address
LS 8 bits of reg
address
Figure 75. I
Figure 76. I
ACK generated by
16
ADE7880
8
0
A
C
K
2
A
C
K
2
A
C
K
C Write Operation of a 32-Bit Register
C Read Operation of a 32-Bit Register
Rev. PrE | Page 71 of 103
15
7
31
Byte3 (MS) of reg
LS 8 bits of reg
Byte2 of reg
address
ACK generated by
begins with the master generating a new start condition
followed by an address byte. The most significant seven bits of
this address byte constitute the address of the ADE7880, and
they are equal to 0111000b. Bit 0 of the address byte is a read/write
bit. Because this is a read operation, it must be set to 1; thus, the
first byte of the read operation is 0x71. After this byte is received,
the ADE7880 generates an acknowledge. Then, the ADE7880
sends the value of the register, and after every eight bits are
received, the master generates an acknowledge. All the bytes
are sent with the most significant bit first. Because registers can
have 8, 16, or 32 bits, after the last bit of the register is received,
the master does not acknowledge the transfer but generates a
stop condition.
ACK generated by
16
ADE7880
A
C
K
8
0
Master
15
A
C
K
A
C
K
Byte2 of reg
7
Byte1of reg
8
A
C
K
7
0
Byte1 of reg
A
C
K
7
Byte0 (LS) of reg
0
A
C
K
7
Byte0 (LS) of reg
ADE7880
0
O
N
A
C
K
O
S
T
P
S
0
A
C
K
O
S
T
P
S