ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 70

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
times after power-up or after a hardware reset, the ADE7880
uses the SPI port until a new hardware reset is executed. This
manipulation of the SS/HSA pin can be accomplished in two
ways. First, use the SS/HSA pin of the master device (that is, the
microcontroller) as a regular I/O pin and toggle it three times.
Second, execute three SPI write operations to a location in the
address space that is not allocated to a specific ADE7880 register
(for example 0xEBFF, where eight bit writes can be executed).
These writes allow the SS
SPI Write Operation section for details on the write protocol
involved.
After the serial port choice is completed, it needs to be locked.
Consequently, the active port remains in use until a hardware
reset is executed in PSM0 normal mode or until a power-down.
If I
CONFIG2 register must be set to 1 to lock it in. From this
moment, the ADE7880 ignores spurious toggling of the
and an eventual switch into using the SPI port is no longer
possible. If the SPI is the active serial port, any write to the
CONFIG2 register locks the port. From this moment, a switch
into using the I
serial port choice is maintained when the ADE7880 changes
PSMx power modes.
The functionality of the ADE7880 is accessible via several on-
chip registers. The contents of these registers can be updated or
read using either the I
provides the state of up to 16 registers representing instantaneous
values of phase voltages and neutral currents, and active, reactive,
and apparent powers.
Communication verification
The ADE7880 includes a set of three registers that allow any
communication via I2C or SPI to be verified. The LAST_OP
(Address 0xEA01), LAST_ADD (Address 0xE9FE) and
LAST_RWDATA registers record the nature, address and data
of the last successful communication respectively. The
LAST_RWDATA register has three separate addresses
depending on the length of the successful communication:
8 bit read/write
16 bit read/write Address 0xE9FF
24 bit read/write Address 0xE5FF
After each successful communication with the ADE7880, the
address of the register that was last accessed is stored in the 16
bit LAST_ADD register (Address 0xE9FE). This is a read only
register that stores the value until the next successful read or
write is complete. The LAST_OP register (Address 0xEA01)
stores the nature of the operation. That is, it indicates whether a
read or a write was performed. If the last operation was a write
the LAST_OP register will store the value 0xCA. If the last
operation was a read the LAST_OP register will store the value
2
C is the active serial port, Bit 1 (I2C_LOCK) of the
2
C port is no longer possible. Once locked, the
Address 0xE7FD
2
C or SPI interfaces. The HSDC port
/HSA pin to toggle three times. See the
SS
pin
Rev. PrE | Page 70 of 103
0x35. The LAST_RWDATA register stores the data that was
written or read from the register. Any unsuccessful read or
write operation will not be reflected in these registers.
When LAST_OP, LAST_ADD and LAST_RWDATA registers
are read, their values are not stored into themselves.
I
The ADE7880 supports a fully licensed I
interface is implemented as a full hardware slave. SDA is the
data I/O pin, and SCL is the serial clock. These two pins are
shared with the MOSI and SCLK pins of the on-chip SPI
interface. The maximum serial clock frequency supported by this
interface is 400 kHz.
The two pins used for data transfer, SDA and SCL, are configured
in a wire-AND’ e d format that allows arbitration in a multi-
master system.
The transfer sequence of an I
initiating a transfer by generating a start condition while the
bus is idle. The master transmits the address of the slave device
and the direction of the data transfer in the initial address transfer.
If the slave acknowledges, the data transfer is initiated. This
continues until the master issues a stop condition, and the bus
becomes idle.
I
The write operation using the I
initiate when the master generates a start condition and consists
in one byte representing the address of the ADE7880 followed
by the 16-bit address of the target register and by the value of
the register.
The most significant seven bits of the address byte constitute
the address of the ADE7880 and they are equal to 0111000b.
Bit 0 of the address byte is a read/write bit. Because this is a
write operation, it has to be cleared to 0; therefore, the first byte
of the write operation is 0x70. After every byte is received, the
ADE7880 generates an acknowledge. As registers can have 8, 16,
or 32 bits, after the last bit of the register is transmitted and the
ADE7880 acknowledges the transfer, the master generates a
stop condition. The addresses and the register content are sent
with the most significant bit first. See Figure 75 for details of the
I
2
2
2
C-Compatible Interface
C write operation.
C Write Operation
Preliminary Technical Data
2
C system consists of a master device
2
C interface of the ADE7880
2
C interface. The I
2
C