ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 90

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
Table 34. STATUS1 Register (Address 0xE503)
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
31:26
Bit Mnemonic
NLOAD
FNLOAD
VANLOAD
ZXTOVA
ZXTOVB
ZXTOVC
ZXTOIA
ZXTOIB
ZXTOIC
ZXVA
ZXVB
ZXVC
ZXIA
ZXIB
ZXIC
RSTDONE
SAG
OI
OV
SEQERR
MISMTCH
Reserved
Reserved
PKI
PKV
CRC
Reserved
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
000 0000
Description
When this bit is set to 1, it indicates that at least one phase entered no load condition
determined by the total active power and apparent power. The phase is indicated in Bits[2:0]
(NLPHASE[x]) in the PHNOLOAD register (see Table 38.)
When this bit is set to 1, it indicates that at least one phase entered no load condition based
on fundamental active and reactive powers. The phase is indicated in Bits[5:3] (FNLPHASE[x])
in PHNOLOAD register (see Table 38 in which this register is described).
When this bit is set to 1, it indicates that at least one phase entered no load condition based
on apparent power. The phase is indicated in Bits[8:6] (VANLPHASE[x]) in the PHNOLOAD
register (see Table 38).
When this bit is set to 1, it indicates a zero crossing on Phase A voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase B voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase C voltage is missing.
When this bit is set to 1, it indicates a zero crossing on Phase A current is missing.
When this bit is set to 1, it indicates a zero crossing on Phase B current is missing.
When this bit is set to 1, it indicates a zero crossing on Phase C current is missing.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase A voltage.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase B voltage.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase C voltage.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase A current.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase B current.
When this bit is set to 1, it indicates a zero crossing has been detected on Phase C current.
In case of a software reset command, Bit 7 (SWRST) is set to 1 in the CONFIG register, or a
transition from PSM1, PSM2, or PSM3 to PSM0, or a hardware reset, this bit is set to 1 at the
end of the transition process and after all registers changed value to default. The IRQ1 pin
goes low to signal this moment because this interrupt cannot be disabled.
When this bit is set to 1, it indicates one of phase voltages entered or exited a sag state. The
phase is indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 37).
When this bit is set to 1, it indicates an overcurrent event has occurred on one of the phases
indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 37).
When this bit is set to 1, it indicates an overvoltage event has occurred on one of the phases
indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 37).
When this bit is set to 1, it indicates a negative-to-positive zero crossing on Phase A voltage
was not followed by a negative-to-positive zero crossing on Phase B voltage but by a
negative-to-positive zero crossing on Phase C voltage.
When this bit is set to 1, it indicates
indicated in the ISUMLVL register.
Reserved. This bit is always set to 1.
Reserved. This bit is always set to 0.
When this bit is set to 1, it indicates that the period used to detect the peak value in the
current channel has ended. The IPEAK register contains the peak value and the phase where
the peak has been detected (see Table 31).
When this bit is set to 1, it indicates that the period used to detect the peak value in the
voltage channel has ended. VPEAK register contains the peak value and the phase where the
peak has been detected (see Table 32).
When this bit is set to 1, it indicates the ADE7880 has computed a different CHECKSUM
relative to the one computed when RUN register was set to 1.
Reserved. These bits are always 0.
Rev. PrE| Page 90 of 103
ISUM
−
INWV
Preliminary Technical Data
>
ISUMLVL
, where ISUMLVL is