ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 91

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 35. MASK0 Register (Address 0xE50A)
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
31:19
Bit Mnemonic
AEHF
FAEHF
Reserved
FREHF
VAEHF
LENERGY
REVAPA
REVAPB
REVAPC
REVPSUM1
REVFRPA
REVFRPB
REVFRPC
REVPSUM2
CF1
CF2
CF3
DREADY
REVPSUM3
HREADY
Reserved
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00 0000 0000
0000
Description
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the total active
energy registers (AWATTHR, BWATTHR, or CWATTHR) changes.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
active energy registers (AFWATTHR, BFWATTHR, or CFWATTHR) changes.
This bit does not manage any functionality.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the fundamental
reactive energy registers (AFVARHR, BFVARHR, or CFVARHR) changes.
When this bit is set to 1, it enables an interrupt when Bit 30 of any one of the apparent
energy registers (AVAHR, BVAHR, or CVAHR) changes.
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end
of an integration over an integer number of half line cycles set in the LINECYC register.
When this bit is set to 1, it enables an interrupt when the Phase A active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C active power identified by
Bit 6 (REVAPSEL) in the ACCMODE register (total or fundamental) changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1
datapath changes sign.
When this bit is set to 1, it enables an interrupt when the Phase A fundamental reactive
power changes sign.
When this bit is set to 1, it enables an interrupt when the Phase B fundamental reactive
power changes sign.
When this bit is set to 1, it enables an interrupt when the Phase C fundamental reactive
power changes sign.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2
datapath changes sign.
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at the
CF1 pin, that is an active low pulse is generated. The interrupt can be enabled even if the
CF1 output is disabled by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of
power used at the CF1 pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register
(see Table 41).
When this bit is set to 1, it enables an interrupt when a high-to-low transition occurs at CF2
pin, that is an active low pulse is generated. The interrupt may be enabled even if the CF2
output is disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power
used at the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 41).
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3
pin, that is an active low pulse is generated. The interrupt may be enabled even if the CF3
output is disabled by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power
used at the CF3 pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 41).
When this bit is set to 1, it enables an interrupt when all periodical (at 8 kHz rate) DSP
computations finish.
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3
datapath changes sign.
When this bit is set to 1, it enables an interrupt when the harmonic block output registers
have been updated. If bit 1 (HRCFG) in CONFIG register is cleared to 0, the interrupt is
triggered every time the harmonic calculations are updated at 8KHz rate. If bit HRCFG is set
to 1, the interrupt is triggered every time the harmonic calculations are updated at 8KHz rate
starting 750msec after the harmonic block setup.
Reserved. These bits do not manage any functionality.
Rev. PrE| Page 91 of 103
ADE7880