ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 34

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
If there is a mismatch between these two quantities, then a
tamper situation may have occurred in the system.
The ADE7880 computes the sum of the phase currents adding
the content of the IAWV, IBWV, and ICWV registers, and
storing the result into the ISUM 28-bit signed register: I
I
frequency), the rate at which the current samples are available,
and Bit 17 (DREADY) in the STATUS0 register is used to signal
when the ISUM register can be read. See the Digital Signal
Processor section for more details on Bit DREADY.
To recover I
following expression:
where:
ADC
scale.
I
Note that the ADE7880 also computes the rms of ISUM and
stores it into NIRMS register when bit 2 (INSEL) in CONGIF3
register is set to 1 (see Current RMS Calculation section for
details).
The ADE7880 computes the difference between the absolute
values of ISUM and the neutral current from the INWV
register, take its absolute value and compare it against the
ISUMLVL threshold. If
is assumed that the neutral current is equal to the sum
of the phase currents, and the system functions correctly. If
have occurred, and Bit 20 (MISMTCH) in the STATUS1 register
is set to 1. An interrupt attached to the flag can be enabled by
setting Bit 20 (MISMTCH) in the MASK1 register. If enabled,
the IRQ1 pin is set low when Status Bit MISMTCH is set to 1.
The status bit is cleared and the
writing to the STATUS1 register with Bit 20 (MISMTCH) set to 1.
ISUMLVL, the positive threshold used in the process, is a 24-bit
signed register. Because it is used in a comparison with an
absolute value, always set ISUMLVL as a positive number,
somewhere between 0x00000 and 0x7FFFFF. ISUMLVL uses
the same scale of the current ADCs outputs, so writing
+5,326,737 (0x514791) to the ISUMLVL register puts the
mismatch detection level at full scale; see the Current Channel
ADC section for details. Writing 0x000000, the default value, or
a negative value, signifies the MISMTCH event is always triggered.
The right value for the application should be written into the
A
FS
ISUM
(t) + I
is the full-scale ADC phase current.
If
If
MAX
I
SUM
B
−
ISUM
ISUM
(t) + I
= 5,928,256, the ADC output when the input is at full
) (
INWV
t
SUM
=
C
(t) value from the ISUM register, use the
ISUM[27:0]
−
−
(t). ISUM is computed every 125 µs (8 kHz
ADC
INWV
INWV
>
ISUMLVL
MAX
ISUM
≤
>
×
ISUMLVL
ISUMLVL
I
FS
−
, then a tamper situation may
IRQ1 pin is set back to high by
INWV
, then MISMTCH = 0
, then MISMTCH = 1
≤
ISUMLVL
, then it
SUM
(t) =
Rev. PrE | Page 34 of 103
ISUMLVL register after power-up or after a hardware/software
reset to avoid continuously triggering MISMTCH events.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
and the DSP works on 28 bits. As presented in Figure 36, ISUM,
the 28-bit signed register, is accessed as a 32-bit register with the
four most significant bits padded with 0s.
Similar to the registers presented in Figure 18, the ISUMLVL
register is accessed as a 32-bit register with four most significant
bits padded with 0s and sign extended to 28 bits.
PHASE COMPENSATION
As described in the Current Channel ADC and Voltage
Channel ADC sections, the datapath for both current and
voltages is the same. The phase error between current and
voltage signals introduced by the ADE7880 is negligible. However,
the ADE7880 must work with transducers that may have
inherent phase errors. For example, a current transformer (CT)
with a phase error of 0.1° to 3° is not uncommon. These phase
errors can vary from part to part, and they must be corrected to
perform accurate power calculations.
The errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE7880 provides a
means of digitally calibrating these small phase errors. The
ADE7880 allows a small time delay or time advance to be
introduced into the signal processing chain to compensate for
the small phase errors.
The phase calibration registers (APHCAL, BPHCAL, and
CPHCAL) are 10-bit registers that can vary the time advance
in the voltage channel signal path from −374.0 µs to +61.5 μs.
Negative values written to the PHCAL registers represent a time
advance whereas positive values represent a time delay. One LSB
is equivalent to 0.976 µs of time delay or time advance (clock
rate of 1.024 MHz). With a line frequency of 60 Hz, this gives
a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the
fundamental. This corresponds to a total correction range of
−8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is
−6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/
1.024 MHz).
Given a phase error of x degrees, measured using the phase
voltage as the reference, the corresponding LSBs are computed
dividing x by the phase resolution (0.0211°/LSB for 60 Hz and
0.0176°/LSB for 50 Hz). Results between −383 and +63 only are
acceptable; numbers outside this range are not accepted. If the
result is negative, the absolute value is written into the PHCAL
Figure 36. The ISUM[27:0] Register is Transmitted As a 32-Bit Word
31
0000
BIT 27 IS A SIGN BIT
28 27
Preliminary Technical Data
28-BIT SIGNED NUMBER
0