ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 68

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

ADE7880
All of the other g
Equation 51, Equation 52, and Equation 53 must be repeated for
j = 1, 2, …, 2272. The value written into the CHECKSUM register
contains the Bit b
Every time a configuration register of the ADE7880 is written or
changes value inadvertently, the bit 25 (CRC) in STATUS1 register
is set to 1 to signal CHECKSUM value has changed. If the bit 25
INTERRUPTS
The ADE7880 has two interrupt pins, IRQ0 and
pins is managed by a 32-bit interrupt mask register, MASK0 and
MASK1, respectively. To enable an interrupt, a bit in the
MASKx register must be set to 1. To disable it, the bit must be
cleared to 0. Two 32-bit status registers, STATUS0 and
STATUS1, are associated with the interrupts. When an interrupt
event occurs in the ADE7880, the corresponding flag in the
interrupt status register is set to a logic 1 (see
34). If the mask bit for this interrupt in the interrupt mask
register is logic 1, then the IRQx logic output goes active low.
The flag bits in the interrupt status register are set irrespective of
the state of the mask bits. To determine the source of the
interrupt, the MCU should perform a read of the corresponding
STATUSx register and identify which bit is set to 1. To erase the flag
in the status register, write back to the STATUSx register with the
flag set to 1. After an interrupt pin goes low, the status register is
read and the source of the interrupt is identified. Then, the status
register is written back without any change to clear the status
flag to 0. The
cancelled.
FB(j) = a
b
b
0
i
(j) = FB(j) AND g
(j) = FB(j) AND g
j – 1
IRQx pin remains low until the status flag is
XOR b
i
i
(2272)
coefficients are equal to 0.
2271
31
i
0
,
(j – 1)
XOR b
i = 0, 1, …, 31.
Array of 2272 bits
i – 1
(j – 1), i = 1, 2, 3, ..., 31
LFSR
g
0
Figure 72. LFSR Generator Used in CHECKSUM Register Calculation
b
0
Table 33
IRQ1. Each of the
g
+
1
Figure 71. CHECKSUM Register Calculation
and Table
b
1
Rev. PrE | Page 68 of 103
(51)
(52)
(53)
g
+
2
0
b
2
(CRC) in MASK1 register is set to 1, then the IRQ1 interrupt pin is
driven low and the status flag CRC in STATUS1 is set to 1. The
status bit is cleared and the
STATUS1 register with the status bit set to 1.
being written, it can be assumed that one of the registers has
changed value and therefore, the ADE7880 has changed
configuration. The recommended response is to initiate a
hardware/software reset that sets the values of all registers to the
default, including the reserved ones, and then reinitialize the
configuration registers.
By default, all interrupts are disabled. However, the RSTDONE
interrupt is an exception. This interrupt can never be masked
(disabled) and, therefore, Bit 15 (RSTDONE) in the MASK1
register does not have any functionality. The
goes low, and Bit 15 (RSTDONE) in the STATUS1 register is set
to 1 whenever a power-up or a hardware/software reset process
ends. To cancel the status flag, the STATUS1 register has to be
written with Bit 15 (RSTDONE) set to 1.
Certain interrupts are used in conjunction with other status
registers. The following bits in the MASK1 register work in
conjunction with the status bits in the PHNOLOAD register:
•
•
•
The following bits in the MASK1 register work with the status bits
in the PHSTATUS register:
•
•
•
When bit CRC in STATUS1 is set to 1 without any register
g
+
3
Bit 0 (NLOAD)
Bit1 (FNLOAD)
Bit 2 (VANLOAD)
Bit 16, (SAG)
Bit 17 (OI)
Bit 18 (OV)
+
a
1767
g
,a
+
31
1766
,...,a
b
2
31
,a
Preliminary Technical Data
generator
1
,a
0
LFSR
IRQ1 pin is set to high by writing to the
+
FB
IRQ1
pin always