ade7880 Analog Devices, Inc., ade7880 Datasheet - Page 89

• Manufacturer Part Number: ade7880
• Description: Polyphase Multifunction Energy Metering Ic With Harmonic Monitoring
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bit
Location
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
31:18
Bit Mnemonic
FREHF
VAEHF
LENERGY
REVAPA
REVAPB
REVAPC
REVPSUM1
REVFRPA
REVFRPB
REVFRPC
REVPSUM2
CF1
CF2
CF3
DREADY
REVPSUM3
HREADY
Reserved
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0000 0000 0000
Description
When this bit is set to 1, it indicates that Bit 30 of any one of the fundamental reactive
energy registers, AFVARHR, BFVARHR, or CFVARHR, has changed.
When this bit is set to 1, it indicates that Bit 30 of any one of the apparent energy
registers (AVAHR, BVAHR, or CVAHR) has changed.
When this bit is set to 1, in line energy accumulation mode, it indicates the end of an
integration over an integer number of half line cycles set in the LINECYC register.
When this bit is set to 1, it indicates that the Phase A active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 0 (AWSIGN) of the PHSIGN register (see Table 43).
When this bit is set to 1, it indicates that the Phase B active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 1 (BWSIGN) of the PHSIGN register (see Table 43).
When this bit is set to 1, it indicates that the Phase C active power identified by Bit 6
(REVAPSEL) in the ACCMODE register (total or fundamental) has changed sign. The sign
itself is indicated in Bit 2 (CWSIGN) of the PHSIGN register (see Table 43).
When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 datapath
has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN register
(see Table 43).
When this bit is set to 1, it indicates that the Phase A fundamental reactive power has
changed sign. The sign itself is indicated in Bit 4 (AFVARSIGN) of the PHSIGN register (see
Table 43).
When this bit is set to 1, it indicates that the Phase B fundamental reactive power has
changed sign. The sign itself is indicated in Bit 5 (BFVARSIGN) of the PHSIGN register (see
Table 43).
When this bit is set to 1, it indicates that the Phase C fundamental reactive power has
changed sign. The sign itself is indicated in Bit 6 (CFVARSIGN) of the PHSIGN register (see
Table 43).
When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 datapath
has changed sign. The sign itself is indicated in Bit 7 (SUM2SIGN) of the PHSIGN register
(see Table 43).
When this bit is set to 1, it indicates a high to low transition has occurred at CF1 pin; that
is, an active low pulse has been generated. The bit is set even if the CF1 output is disabled
by setting Bit 9 (CF1DIS) to 1 in the CFMODE register. The type of power used at the CF1
pin is determined by Bits[2:0] (CF1SEL[2:0]) in the CFMODE register (see Table 41).
When this bit is set to 1, it indicates a high-to-low transition has occurred at the CF2 pin;
that is, an active low pulse has been generated. The bit is set even if the CF2 output is
disabled by setting Bit 10 (CF2DIS) to 1 in the CFMODE register. The type of power used at
the CF2 pin is determined by Bits[5:3] (CF2SEL[2:0]) in the CFMODE register (see Table 41).
When this bit is set to 1, it indicates a high-to-low transition has occurred at CF3 pin; that
is, an active low pulse has been generated. The bit is set even if the CF3 output is disabled
by setting Bit 11 (CF3DIS) to 1 in the CFMODE register. The type of power used at the CF3
pin is determined by Bits[8:6] (CF3SEL[2:0]) in the CFMODE register (see Table 41).
When this bit is set to 1, it indicates that all periodical (at 8 kHz rate) DSP computations
have finished.
When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 datapath
has changed sign. The sign itself is indicated in Bit 8 (SUM3SIGN) of the PHSIGN register
(see Table 43).
When this bit is set to 1, it indicates the harmonic block output registers have been
updated. If bit 1 (HRCFG) in CONFIG register is cleared to 0, this flag is set to 1 every time
the harmonic block output registers are updated at 8KHz rate. If bit HRCFG is set to 1, the
HREADY flag is set to 1 every time the harmonic block output registers are updated at
8KHz rate starting 750msec after the harmonic block setup .
Reserved. These bits are always 0.
Rev. PrE| Page 89 of 103
ADE7880