R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 622
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Section 15 Watchdog Timer (WDT)
Note:
Rev. 2.00 Sep. 16, 2009 Page 592 of 1036
REJ09B0414-0200
Bit
7
6
5
4, 3
2
1
0
*
Bit Name
OVF
WT/IT
TME
CKS2
CKS1
CKS0
Only 0 can be written to this bit, to clear the flag.
Initial
Value
0
0
0
All 1
0
0
0
R/W
R/(W)* Overflow Flag
R/W
R/W
R
R/W
R/W
R/W
Description
Indicates that TCNT has overflowed in interval timer
mode. Only 0 can be written to this bit, to clear the flag.
[Setting condition]
When TCNT overflows in interval timer mode (changes
from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0
to OVF
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
Timer Enable
When this bit is set to 1, TCNT starts counting. When this
bit is cleared, TCNT stops counting and is initialized to
H'00.
Reserved
These are read-only bits and cannot be modified.
Clock Select 2 to 0
Select the clock source to be input to TCNT. The overflow
cycle for Pφ = 20 MHz is indicated in parentheses.
000: Clock Pφ/2 (cycle: 25.6 µs)
001: Clock Pφ/64 (cycle: 819.2 µs)
010: Clock Pφ/128 (cycle: 1.6 ms)
011: Clock Pφ/512 (cycle: 6.6 ms)
100: Clock Pφ/2048 (cycle: 26.2 ms)
101: Clock Pφ/8192 (cycle: 104.9 ms)
110: Clock Pφ/32768 (cycle: 419.4 ms)
111: Clock Pφ/131072 (cycle: 1.68 s)
When TCNT overflows, an interval timer interrupt
(WOVI) is requested.
When TCNT overflows, the WDTOVF signal is output.
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