UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 254

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
6.6.3 Example of controlling subsystem clock
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The following describes examples of setting procedures for the following cases.
(1) When oscillating XT1 clock
(2) When using external subsystem clock
(3) When using subsystem clock as CPU clock
(4) When stopping subsystem clock
The following two types of subsystem clocks
• XT1 clock:
• External subsystem clock: External clock is input to the EXCLKS pin.
When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins.
Note
Cautions 1. The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release.
(1) Example of setting procedure when oscillating the XT1 clock
(2) Example of setting procedure when using the external subsystem clock
<1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers)
<2> Waiting for the stabilization of the subsystem clock oscillation
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
<1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
The 78K0/KB2 is not provided with a subsystem clock.
Remark
When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from port
mode to XT1 oscillation mode.
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
registers)
When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port
mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124 pins.
2. Do not start the peripheral hardware operation with the external clock from peripheral hardware
XTSTART
XTSTART
pins when the internal high-speed oscillation clock and high-speed system clock are stopped
while the CPU operates with the subsystem clock, or when in the STOP mode.
operating.
operating.
0
1
0
×: don’t care
EXCLKS
EXCLKS
0
×
1
Crystal/ceramic resonator is connected across the XT1 and XT2 pins.
OSCSELS
OSCSELS
1
×
1
Note
XT1 oscillation mode
External clock input
mode
Subsystem Clock Pin
Subsystem Clock Pin
Operation Mode of
Operation Mode of
are available.
Crystal/ceramic resonator connection
I/O port
P123/XT1 Pin
P123/XT1 Pin
CHAPTER 6 CLOCK GENERATOR
External clock input
EXCLKS Pin
P124/XT2/
EXCLKS Pin
P124/XT2/
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