UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 263

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already
Caution
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(B) → (E)
(C) → (F)
(D) → (G)
Status Transition
(D) → (C) (X1 clock: 1 MHz ≤ f
10 MHz)
(D) → (C) (external main clock: 1 MHz ≤
f
(D) → (C) (X1 clock: 10 MHz < f
20 MHz)
(D) → (C) (external main clock: 10 MHz <
f
XH
XH
≤ 10 MHz
≤ 20 MHz)
Note The 78K0/KB2 is not provided with a subsystem clock.
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
Note The 78K0/KB2 is not provided with a subsystem clock.
Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18.
been set.
(Setting sequence of SFR registers)
Note
Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL
SPECIFICATIONS ((A2) GRADE PRODUCTS: T
Setting Flag of SFR Register
2. EXCLK, OSCSEL, AMPH: Bits 7, 6, and 0 of the clock operation mode select register (OSCCTL)
Status Transition
MSTOP:
XSEL, MCM0:
CSS:
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (4/5)
XH
XH
≤
≤
AMPH
Unnecessary if these registers
0
0
1
1
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
Note
Executing HALT instruction
are already set
EXCLK
0
1
0
1
OSCSEL
A
= −40 to +125°C)).
1
1
1
1
with the high-speed
MSTOP
Unnecessary if the
CPU is operating
system clock
0
0
0
0
Setting
Must not be
Must not be
Note
CHAPTER 6 CLOCK GENERATOR
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Note
XSEL
Unnecessary if this register
1
1
1
1
Note
is already set
MCM0
1
1
1
1
CSS
0
0
0
0
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