UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 523

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FF97H
(7) Automatic data transfer address count register 0 (ADTC0)
(8) Port mode register 14 (PM14)
Address: FF2EH
Symbol
PM14
Symbol
ADTC0
This is a register used to indicate buffer RAM addresses during automatic transfer. When automatic transfer is
stopped, the data position when transfer stopped can be ascertained by reading ADTC0 register value.
This register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H. However, reading from ADTC0 is prohibited when bit 0
(TSF0) of serial status register 0 (CSIS0) = 1.
This register sets port 14 input/output in 1-bit units.
When using P142/SCKA0 pin as the clock output of the serial interface, clear PM142 to 0 and set the output latch
of P142 to 1.
When using P144/SOA0 and P145/STB0 pins as the data output or strobe output of the serial interface, clear
PM144, PM145, and the output latches of P144 and P145 to 0.
When using P141/BUSY0, P142/SCKA0, and P143/SIA0 pins as the busy input, clock input, or data input of the
serial interface, set PM141, PM142, and PM143 to 1. At this time, the output latches of P141, P142, and P143
may be 0 or 1.
PM14 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 17-8. Format of Automatic Data Transfer Address Count Register 0 (ADTC0)
PM14n
7
1
0
1
After reset: 00H
7
0
After reset: FFH
Output mode (output buffer on)
Input mode (output buffer off)
6
1
Figure 17-9. Format of Port Mode Register 14 (PM14)
6
0
R
PM145
5
R/W
P14n pin I/O mode selection (n = 0 to 5)
5
0
PM144
4
ADTC04
PM143
4
3
ADTC03
PM142
CHAPTER 17 SERIAL INTERFACE CSIA0
2
3
PM141
ADTC02
1
2
PM140
0
ADTC01
1
ADTP00
0
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