UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 695

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
oscillation clock (f
(when X1 oscillation
Internal reset signal
Notes 1.
Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 25
Remark V
Internal high-speed
system clock (f
V
V
DDPOC
Supply voltage
POC
High-speed
is selected)
= 1.59 V (TYP.)
= 2.7 V (TYP.)
2.
3.
1.8 V
CPU
V
(V
RH
XH
2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
Note 1
V
The guaranteed operation range for the standard and (A) grade products is 1.8 V ≤ V
≤ V
to the reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input a
low level to the RESET pin.
The CPU clock can be switched from the internal high-speed oscillation clock to the high-speed system
clock or subsystem clock
oscillation stabilization time. To use the XT1 clock
of the stabilization time.
The 78K0/KB2 is not provided with subsystem clock and XT1 clock.
LVI
POC
DD
0 V
LVI
)
)
Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
)
Operation
LOW-VOLTAGE DETECTOR).
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms,
the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated before
reset processing.
: LVI detection voltage
: POC detection voltage
DD
stops
≤ 5.5 V for the (A2) grade products. To set the voltage range below the guaranteed operation range
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
Note 3
and Low-Voltage Detector (2/2)
. To use the X1 clock, use the OSTC register to confirm the lapse of the
Note 2
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
Note 3
specified by software.
Starting oscillation is
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
, use the timer function for confirmation of the lapse
Note 2
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
Note 2
DD
≤ 5.5 V, and 2.7 V
Operation stops
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