UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 570

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5 I
Figure 18-12 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I
bus’s serial data bus.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that
receives 8-bit data).
level period can be extended and a wait can be inserted.
18.5.1 Start conditions
start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device when
starting a serial transfer. When the device is used as a slave, start conditions can be detected.
detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of IICS0 is set
(to 1).
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The following section describes the I
The master device generates the start condition, slave address, and stop condition.
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0’s low
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level. The
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has been
2
C Bus Definitions and Control Methods
SDA0
SCL0
Start
condition
Figure 18-12. I
Address R/W ACK
1-7
SDA0
SCL0
2
C bus’s serial data communication format and the signals used by the I
Figure 18-13. Start Conditions
8
H
2
C Bus Serial Data Transfer Timing
9
Data
1-8
ACK
9
CHAPTER 18 SERIAL INTERFACE IIC0
Data
1-8
ACK
9
Stop
condition
2
C bus.
570
2
C