UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 949

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Clock
generator
operation
when power
supply
voltage is
turned on
Controlling
high-speed
system clock
Controlling
internal low-
speed
oscillation
clock
Function
X1/P121 and
X2/EXCLK/P122
X1 clock
External main
system clock
Main system
clock
High-speed
system clock
Internal high-
speed oscillation
clock
XT1/P123,
XT2/EXCLKS/
P124
External clock
from peripheral
hardware pins
XT1 clock,
external
subsystem clock
Subsystem clock
Internal low-
speed oscillation
clock
Details of
Function
−
It is not necessary to wait for the oscillation stabilization time when an external clock
input from the EXCLK and EXCLKS pins is used.
A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the power
supply voltage reaches 1.59 V (TYP.). If the supply voltage rises from
1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation
stabilization time of 0 to 5.39 ms is automatically generated before reset processing.
The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset
release.
Do not change the value of EXCLK and OSCSEL while the X1 clock is operating.
Set the X1 clock after the supply voltage has reached the operable voltage of the
clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD
PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2) GRADE
PRODUCTS : T
Do not change the value of EXCLK and OSCSEL while the external main systerm
clock is operating.
Set the external main system clock after the supply voltage has reached the operable
voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS
(STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL SPECIFICATIONS ((A2)
GRADE PRODUCTS : T
If the high-speed system clock is selected as the main system clock, a clock other
than the high-speed system clock cannot be set as the peripheral hardware clock.
Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
peripheral hardware that is operating on the high-speed system clock.
Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition,
stop peripheral hardware that is operating on the internal high-speed oscillation
clock.
The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset
release.
Do not start the peripheral hardware operation with the external clock from peripheral
hardware pins when the internal high-speed oscillation clock and high-speed system
clock are stopped while the CPU operates with the subsystem clock, or when in the
STOP mode.
Do not change the value of XTSTART, EXCLKS, and OSCSELS while the
subsystem clock is operating.
Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the
watch timer if it is operating on the subsystem clock.
The subsystem clock oscillation cannot be stopped using the STOP instruction.
If “Internal low-speed oscillator cannot be stopped” is selected by the option byte,
oscillation of the internal low-speed oscillation clock cannot be controlled.
A
= • 40 to +125°C)).
A
= • 40 to +125°C)).
Cautions
APPENDIX D LIST OF CAUTIONS
pp. 246,
247
p. 247
p. 248
p. 249
p. 249
p. 249
p. 249
p. 250
p. 251
p. 253
p. 254
p. 254
p. 254
p. 255
p. 255
p. 256
Page
(6/30)
949