UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 539

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
SCKA0
ACSIIF
(b) Automatic transmission mode
SOA0
TSF0
Cautions 1. Because, in the automatic transmission mode, the automatic transmit/receive function
Remark
In this mode, the specified data is transmitted in 8-bit unit.
Serial communication is started when bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) is set to 1 while bit 7
(CSIAE0), bit 6 (ATE0), and bit 3 (TXEA0) of serial operation mode specification register 0 (CSIMA0) are set
to 1.
When the final byte has been transmitted, an interrupt request flag (ACSIIF) is set. The termination of
automatic transmission can also be judged by bit 0 (TSF0) of serial status register 0 (CSIS0).
If a receive
BUSY0/BUZ/INTP7/P141, and STB0/P145 pins can be used as normal I/O port pins.
Figure 17-17 shows the example of the automatic transmission mode operation timing, and Figure 17-18
shows the operation flowchart.
Figure 17-17. Example of Automatic Transmission Mode Operation Timing
D7 D6 D5 D4 D3 D2 D1 D0
ACSIIF: Interrupt request flag
TSF0:
2. If an access to the buffer RAM by the CPU conflicts with an access to the buffer RAM by
reads data from the internal buffer RAM after 1-byte transmission, an interval is inserted
until the next transmission. As the buffer RAM read is performed at the same time as
CPU processing, the interval is dependent upon the value of automatic data transfer
interval specification register 0 (ADTI0) and the set values of bits 5 and 4 (STBE0,
BUSYE0) of serial status register 0 (CSIS0) (see (5) Automatic transmit/receive interval
time).
serial interface CSIA0 during the interval period, the interval time specified by automatic
data transfer interval specification register 0 (ADTI0) may be extended.
operation, busy control
Bit 0 of serial status register 0 (CSIS0)
Interval
and strobe
D7 D6 D5 D4 D3 D2 D1 D0
CHAPTER 17 SERIAL INTERFACE CSIA0
control are
not executed, the SIA0/P143,
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