UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 967

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Interrupt
function
Key
interrupt
function
Standby
function
Function
EGP, EGN:
External interrupt
rising edge, falling
edge enable
registers
Software interrupt
request
BRK instruction
KRM: Key return
mode register
Standby function
OSTC: Oscillation
stabilization time
counter status
register
OSTS: Oscillation
stabilization time
select register
Details of
Function
Be sure to clear bits 6 and 7 of EGP and EGN to 0 in 78K0/KB2, and the 38-pin and
44-pin products of 78K0/KC2.
Be sure to clear bit 7 of EGP and EGN to 0 in 78K0/KD2, and the 48-pin products of
78K0/KC2.
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Do not use the RETI instruction for restoring from the software interrupt.
The BRK instruction is not one of the above-listed interrupt request hold instructions.
However, the software interrupt activated by executing the BRK instruction causes the
IE flag to be cleared. Therefore, even if a maskable interrupt request is generated
during execution of the BRK instruction, the interrupt request is not acknowledged.
If any of the KRMn bits used is set to 1, set bit n (PU7n) of the corresponding pull-up
resistor register 7 (PU7) to 1.
If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts
and then change the KRM register. Clear the interrupt request flag and enable
interrupts.
The bits not used in the key interrupt mode can be used as normal ports.
For the 38-pin products of 78K0/KC2, be sure to set bits 2 to 7 of KRM to “0”. For the
44-pin and 48-pin products of 78K0/KC2, be sure to set bits 4 to 7 of KRM to “0”.
The STOP mode can be used only when the CPU is operating on the main system
clock. The subsystem clock oscillation cannot be stopped. The HALT mode can be
used when the CPU is operating on either the main system clock or the subsystem
clock.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
The following sequence is recommended for operating current reduction of the A/D
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE)
of the A/D converter mode register (ADM) to 0 to stop the A/D conversion operation,
and then execute the STOP instruction.
After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal high-
speed oscillation clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by OSTS
is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before
executing the STOP instruction.
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal high-
speed oscillation clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by OSTS
is set to OSTC after STOP mode is released.
OSTS
OSTS
Cautions
APPENDIX D LIST OF CAUTIONS
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