UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 617

no-image

UPD78F0500AMC-CAB-AX

Manufacturer Part Number
UPD78F0500AMC-CAB-AX
Description
MCU 8BIT 30SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet

Specifications of UPD78F0500AMC-CAB-AX

Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(3) Stop condition
Notes 1. Write data to IIC0, not setting WREL0, in order to cancel a wait state during master transmission.
WREL0
INTIIC0
WREL0
INTIIC0
ACKD0
ACKE0
MSTS0
ACKD0
ACKE0
MSTS0
WTIM0
WTIM0
Transfer lines
Processing by slave device
Processing by master device
STD0
SPD0
TRC0
SDA0
STD0
SPD0
TRC0
SPT0
SCL0
SPT0
STT0
STT0
IIC0
IIC0
2. To cancel slave wait, write “FFH” to IIC0 or set WREL0.
H
H
H
H
L
L
L
L
L
Receive
Transmit
(When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
IIC0
IIC0
D7
Note 2
1
Figure 18-27. Example of Master to Slave Communication
D6
FFH Note 2
data Note 1
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
ACK
9
CHAPTER 18 SERIAL INTERFACE IIC0
IIC0
Note 2
condition
Stop
FFH Note 2
(When SPIE0 = 1)
(When SPIE0 = 1)
condition
Start
IIC0
AD6
1
AD5
address
2
617

Related parts for UPD78F0500AMC-CAB-AX