UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 587

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(2) Master operation in multi-master system
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period of
one frame). If the SDA0 pin is constantly at low level, decide whether to release the I
pins = high level) in conformance with the specifications of the product that is communicating.
1
No
ACKE0 = WTIM0 = SPIE0 = 1
Setting STCEN and IICRSV
Checking bus status
Enables reserving
interrupt occurs?
Master operation
communication.
IICCL0
SVA0
IICC0
IICX0
IICF0
IICRSV = 0?
Setting port
SPD0 = 1?
SPIE0 = 1
IICE0 = 1
INTIIC0
START
starts?
A
Yes
Yes
Yes
Yes
(Communication start request)
0XH
XXH
0XH
XXH
XXH
Bus status is
being checked.
Waiting to be specified as a slave by other master
Waiting for a communication start request (depends on user program)
Figure 18-24. Master Operation in Multi-Master System (1/3)
Note
Disables reserving
communication.
(No communication start request)
No
No
No
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Sets each pin in the I
Releases the bus for a specific period.
Slave operation
B
STCEN = 1?
2
C mode (see 18.3 (7) Port mode register 6 (PM6)).
Yes
interrupt occurs?
Slave operation
SPIE0 = 0
INTIIC0
Yes
No
Waits for a communication request.
No
CHAPTER 18 SERIAL INTERFACE IIC0
interrupt occurs?
SPD0 = 1?
SPT0 = 1
INTIIC0
Yes
Yes
No
No
2
Waits for detection
of the stop condition.
Prepares for starting
communication
(generates a stop condition).
Slave operation
C bus (SCL0 and SDA0
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