UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 262

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Status Transition
(C) → (B)
(C) → (D) (XT1 clock)
(C) → (D) (external subsystem clock)
Status Transition
(D) → (B)
Status Transition
Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18.
Note The 78K0/KB2 is not provided with a subsystem clock.
Note The 78K0/KB2 is not provided with a subsystem clock.
2. MCM0:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL)
RSTS, RSTOP:
XTSTART, CSS:
×:
Setting Flag of SFR Register
Setting Flag of SFR Register
Setting Flag of SFR Register
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (3/5)
Bit 0 of the main clock mode register (MCM)
Bits 7 and 0 of the internal oscillation mode register (RCM)
Bits 6 and 4 of the processor clock control register (PCC)
Don’t care
Unnecessary if the CPU is operating
XTSTART
with the internal high-speed oscillation clock
RSTOP
with the internal high-speed
0
1
0
Unnecessary if the CPU is operating
0
RSTOP
Unnecessary if the CPU is operating
oscillation clock
0
with the subsystem clock
EXCLKS
Confirm this flag
0
×
1
RSTS
is 1.
Confirm this flag is 1.
OSCSELS
RSTS
CHAPTER 6 CLOCK GENERATOR
1
×
1
Unnecessary if
XSEL is 0
MCM0
Note
0
↑
Unnecessary
Stabilization
Waiting for
Oscillation
Necessary
MCM0
0
CSS
0
CSS
1
1
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