UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 525

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
17.4.2 3-wire serial I/O mode
specification register 0 (CSIMA0) is cleared to 0.
input (SIA0) lines.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
The one-byte data transmission/reception is executed in the mode in which bit 6 (ATE0) of serial operation mode
The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers with a clocked serial interface.
In this mode, communication is executed by using three lines: serial clock (SCKA0), serial output (SOA0), and serial
(1) Registers used
• Serial operation mode specification register 0 (CSIMA0)
• Serial status register 0 (CSIS0)
• Divisor selection register 0 (BRGCA0)
• Port mode register 14 (PM14)
• Port register 14 (P14)
Notes 1. Bits 7, 6, and 4 to 1 (CSIAE0, ATE0, MASTER0, TXEA0, RXEA0, and DIR0) are used. Setting of bit 5
The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows.
<1> Set bit 6 (CKS00) of the CSIS0 register (see Figure 17-3)
<2> Set the BRGCA0 register (see Figure 17-5)
<3> Set bits 4 to 1 (MASTER0, TXEA0, RXEA0, and DIR0) of the CSIMA0 register (see Figure 17-2).
<4> Set bit 7 (CSIAE0) of the CSIMA0 register to 1 and clear bit 6 (ATE0) to 0.
<5> Write data to serial I/O shift register 0 (SIOA0). → Data transmission/reception is started
Notes 1. This register does not have to be set when the slave mode is specified (MASTER0 = 0).
Caution Take relationship with the other party of communication when setting the port mode register
2. Only bit 0 (TSF0) and bit 6 (CKS00) are used.
2. Write dummy data to SIOA0 only for reception.
(ATM0) is invalid.
and port register.
Note 2
Note 1
.
Note 1
CHAPTER 17 SERIAL INTERFACE CSIA0
Note 1
.
Note 2
.
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