UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 700

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FFBEH
Symbol
LVIM
Notes 1.
Cautions 1. To stop LVI, follow either of the procedures below.
LVION
LVION
LVISEL
LVIMD
<7>
LVIF
2.
3.
4.
0
1
0
1
0
1
0
1
Notes 3, 4
After reset: 00H
Note 3
Note 3
2. Input voltage from external input pin (EXLVI) must be EXLVI < V
This bit is cleared to 00H upon a reset other than an LVI reset.
Bit 0 is read-only.
LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset. These
are not cleared to 0 in the case of an LVI reset.
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to
wait for an operation stabilization time (10
is stabilized. After operation has stabilized, the external input of 200
width: 200
until LVIF is set (1).
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Disables operation
Enables operation
Detects level of supply voltage (V
Detects level of input voltage from external input pin (EXLVI)
• LVISEL = 0: Generates an internal interrupt signal when the supply voltage (V
• LVISEL = 1: Generates an interrupt signal when the input voltage from an external
• LVISEL = 0: Generates an internal reset signal when the supply voltage (V
• LVISEL = 1: Generates an internal reset signal when the input voltage from an
• LVISEL = 0: Supply voltage (V
• LVISEL = 1: Input voltage from external input pin (EXLVI) ≥ detection voltage (V
• LVISEL = 0: Supply voltage (V
• LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (V
Figure 25-2. Format of Low-Voltage Detection Register (LVIM)
6
0
μ
Note 1
s (MIN.)) is required from when a state below LVI detection voltage has been entered,
Low-voltage detection operation mode (interrupt/reset) selection
lower than the detection voltage (V
V
input pin (EXLVI) drops lower than the detection voltage (V
V
detection voltage (V
external input pin (EXLVI) < detection voltage (V
reset signal when EXLVI ≥ V
disabled
or when operation is disabled
5
0
LVI
EXLVI
R/W
or higher (V
) or when EXLVI becomes V
Note 2
Enables low-voltage detection operation
4
0
Voltage detection selection
DD
Low-voltage detection flag
DD
DD
DD
≥ V
) ≥ detection voltage (V
) < detection voltage (V
LVI
)
LVI
) and releases the reset signal when V
).
3
0
EXLVI
μ
s (MIN.)) from when LVION is set to 1 until operation
.
CHAPTER 25 LOW-VOLTAGE DETECTOR
EXLVI
LVI
LVISEL
) (V
<2>
or higher (EXLVI ≥ V
DD
LVI
LVI
< V
), or when operation is
)
LVI
EXLVI
) or when V
LVIMD
<1>
) and releases the
EXLVI
EXLVI
DD
DD
DD
DD
μ
) (EXLVI <
becomes
).
≥ V
.
s (MIN.) (Minimum pulse
LVIF
) <
<0>
DD
LVI
) drops
EXLVI
EXLVI
.
),
)
700