UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 632

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Maskable
Software
Reset
Interrupt
Type
Notes 1.
External
Internal
External
Internal
Internal/
External
2.
3.
4.
5.
6.
−
−
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1.
The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 28 indicates the lowest priority.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
48-pin products only.
INTIIC0:
INTIIC0/INTDMU: products with the flash memory of 48 KB or more
Products with the flash memory of 48 KB or more only.
Configuration
Type
Basic
(C)
(A)
(B)
(A)
(D)
−
Note 1
Priority
Default
20
21
22
23
24
25
26
27
28
−
−
products with the flash memory of 32 KB or less
Note 2
INTKR
INTWT
INTP6
INTP7
INTIIC0/
INTDMU
INTCSI11 End of CSI11 communication
INTTM001 Match between TM01 and CR001
INTTM011 Match between TM01 and CR011
INTACSI
BRK
RESET
POC
LVI
WDT
Table 20-1. Interrupt Source List (2/2)
Name
Key interrupt detection
Watch timer overflow
Pin input edge detection
End of IIC0 communication/end of
multiply/divide operation
(when compare register is specified),
TI011 pin valid edge detection
(when capture register is specified)
(when compare register is specified),
TI001 pin valid edge detection
(when capture register is specified)
End of CSIA0 communication
BRK instruction execution
Reset input
Power-on clear
Low-voltage detection
WDT overflow
Interrupt Source
Trigger
Note 3
CHAPTER 20 INTERRUPT FUNCTIONS
Address
002CH
002EH
003AH
003CH
003EH
0030H
0032H
0034H
0036H
0038H
0000H
Vector
Table
Note 5
K
B
2
−
−
−
−
√
−
−
−
−
√
√
Note 4
Note 5
C
K
2
√
√
√
−
√
−
−
−
−
√
√
Note 5
D
K
2
√
√
√
−
√
−
−
−
−
√
√
Note 5
Note 6
Note 6
Note 6
K
E
2
√
√
√
√
√
√
√
√
−
√
√
K
F
2
√
√
√
√
√
√
√
√
√
√
√
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