UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 537

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
FA1FH
FA05H
FA00H
(ii) Completion of transmission/reception (see Figure 17-16)
Figure 17-15. Internal Buffer RAM Operation in Automatic Transmission/Reception Mode
<1> When transmission/reception of the sixth byte is completed, receive data 6 (R6) is transferred from
<2> When the value of ADPT0 and that of ADTC0 match, the automatic transmission/reception ends,
FA1FH
FA05H
FA00H
Transmit data 6 (T6)
Transmit data 5 (T5)
Transmit data 4 (T4)
Transmit data 3 (T3)
Transmit data 2 (T2)
Transmit data 1 (T1)
SIOA0 to the internal buffer RAM and ADTC0 is incremented.
and an interrupt request flag (ACSIIF) is set (INTACSI is generated). ADTC0 and bit 0 (TSF0) of
serial status register 0 (CSIS0) are cleared to 0.
Transmit data 6 (T6)
Transmit data 5 (T5)
Transmit data 4 (T4)
Transmit data 3 (T3)
Transmit data 2 (T2)
Receive data 1 (R1)
<3> Starting of 2nd byte transmission/reception
<2> End of 1st byte transmission/reception
(Starting Transmission/Reception) (2/2)
+1
Receive data 1 (R1)
CHAPTER 17 SERIAL INTERFACE CSIA0
5
0
0
Receive data 1 (R1)
5
1
0
SIOA0
ADTP0
ADTC0
ACSIIF
SIOA0
ADTP0
ADTC0
ACSIIF
Data reception
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