UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 970

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Option
byte
Flash
memory
Function
0081H/1081H
0084H/1084H
0080H/1080H
0081H/1081H
IMS: Internal
memory size
switching register,
IXS: internal
expansion RAM
size switching
register
Operation clock
Processing of X1,
P31 pins
Selecting
communication
mode
Security Settings
Details of
Function
POCMODE can only be written by using a dedicated flash memory programmer. It
cannot be set during self-programming or boot swap operation during self-
programming. However, because the value of 1081H is copied to 0081H during the
boot swap operation, it is recommended to set a value that is the same as that of
0081H to 1081H when the boot swap function is used.
Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not
equipped with the on-chip debug function (
to 1084H because 0084H and 1084H are switched during the boot swap operation.
To use the on-chip debug function with a product equipped with the on-chip debug
function (
is the same as that of 0084H to 1084H because 0084H and 1084H are switched during
the boot swap operation.
The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
is prohibited.
Setting WINDOW1 = WINDOW0 = 0 is prohibited when using the watchdog timer at
1.8 V ≤ V
The watchdog timer continues its operation during self-programming and EEPROM
emulation of the flash memory. During processing, the interrupt acknowledge time is
delayed. Set the overflow time and window size taking this delay into consideration.
If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied
to the watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0
(LSRSTOP) of the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count
clock is supplied to 8-bit timer H1 even in the HALT/STOP mode
Be sure to clear bit 7 to 0.
Be sure to clear bits 7 to 1 to “0”.
Be sure to set each product to the values shown in Table 27-1 after a reset release.
Be sure to set each product to the values shown in Table 27-2 after a reset release.
To set the memory size, set IMS and then IXS. Set the memory size so that the
internal ROM and internal expansion RAM areas do not overlap.
Only the internal high-speed oscillation clock (f
Only the X1 clock (f
is used.
For the product with an on-chip debug function (
connect P31/INTP2/OCD1A and P121/X1/OCD0A as follows when writing the flash
memory with a flash memory programmer.
• P31/INTP2/OCD1A: Connect to EV
• P121/X1/OCD0A: Connect to V
When UART6 is selected, the receive clock is calculated based on the reset command
sent from the dedicated flash memory programmer after the FLMD0 pulse has been
received.
After the security setting for the batch erase is set, erasure cannot be performed for the
device. In addition, even if a write command is executed, data different from that which
has already been written to the flash memory cannot be written, because the erase
command is disabled.
If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of that
device will not be rewritten, and the device will not be erased in batch.
μ
DD
PD78F05xxD and 78F05xxDA), set 02H or 03H to 0084H. Set a value that
< 2.7 V.
X
) or external main system clock (f
SS
via a resistor.
SS
Cautions
via a resistor.
μ
PD78F05xx and 78F05xxA). Also set 00H
RH
μ
) can be used when CSI10 is used.
PD78F05xxD and 78F05xxDA),
APPENDIX D LIST OF CAUTIONS
EXCLK
) can be used when UART6
p. 716
p. 717
p. 717
p. 718
p. 718
p. 718
p. 718
p. 718
p. 719
p. 721
p. 722
pp. 721,
723
p. 731
p. 731
p. 731
p. 733
p. 735
p. 735
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