UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 952

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
16-bit
timer/event
counters
00, 01
8-bit
timer/event
counters
50, 51
Function
ES0n0, ES0n1
Re-triggering
one-shot pulse
OVF0n
One-shot pulse
output
TI00n
TI00n, TI01n
INTTM00n,
INTTM01n
CRC0n1 = 1
Specifying valid
edge after reset
Sampling clock
for eliminating
noise
TI00n/TI01n
Reading of TM0n TM0n can be read without stopping the actual counter, because the count values
CR5n: 8-bit timer
compare register
5n
Details of
Function
Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and
TMC0n2 = 00). Set the valid edge by using ES0n0 and ES0n1.
Make sure that the trigger is not generated while an active level is being output in the
one-shot pulse output mode. Be sure to input the next trigger after the current active
level is output.
The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows.
Select the clear & start mode entered upon a match between TM0n and CR00n.
→ Set CR00n to FFFFH.
→When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H
Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count
clock is counted (before the value of TM0n becomes 0001H), it is set to 1 again and
clearing is invalid.
One-shot pulse output operates correctly in the free-running timer mode or the clear
& start mode entered by the TI00n pin valid edge. The one-shot pulse cannot be
output in the clear & start mode entered upon a match between TM0n and CR00n.
When the valid edge of TI00n is specified as the count clock, the capture register for
which TI00n is specified as a trigger does not operate correctly.
To accurately capture the count value, the pulse input to the TI00n and TI01n pins as
a capture trigger must be wider than two count clocks selected by PRM0n (see
Figure 7-9).
The capture operation is performed at the falling edge of the count clock but the
interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of the
next count clock (see Figure 7-9).
When the count value of the TM0n register is captured to the CR00n register in the
phase reverse to the signal input to the TI00n pin, the interrupt signal (INTTM00n) is
not generated after the count value is captured. If the valid edge is detected on the
TI01n pin during this operation, the capture operation is not performed but the
INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n
signal when the external interrupt is not used.
If the operation of the 16-bit timer/event counter 0n is enabled after reset and while
the TI00n or TI01n pin is at high level and when the rising edge or both the edges are
specified as the valid edge of the TI00n or TI01n pin, then the high level of the TI00n
or TI01n pin is detected as the rising edge. Note this when the TI00n or TI01n pin is
pulled up. However, the rising edge is not detected when the operation is once
stopped and then enabled again.
The sampling clock for eliminating noise differs depending on whether the valid edge
of TI00n is used as the count clock or capture trigger. In the former case, the
sampling clock is fixed to f
used for sampling.
When the signal input to the TI00n pin is sampled and the valid level is detected two
times in a row, the valid edge is detected. Therefore, noise having a short pulse
width can be eliminated (see Figure 7-9).
The signal input to the TI00n/TI01n pin is not acknowledged while the timer is
stopped, regardless of the operation mode of the CPU.
captured to the buffer are fixed when it is read. The buffer, however, may not be
updated when it is read immediately before the counter counts up, because the buffer
is updated at the timing the counter counts up.
In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 =
0), do not write other values to CR5n during operation.
In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock
selected by TCL5n) or more.
PRS
. In the latter, the count clock selected by PRM0n is
Cautions
APPENDIX D LIST OF CAUTIONS
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