UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 694

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
oscillation clock (f
(when X1 oscillation
Internal reset signal
Internal high-speed
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 25 LOW-
Remark V
V
system clock (f
POC
= 1.59 V (TYP.)
High-speed
is selected)
Supply voltage
1.8 V
5.
2.
3.
4.
6.
Notes 1, 2, 3
CPU
RH
XH
VOLTAGE DETECTOR).
V
(V
V
)
)
0 V
Operation
The guaranteed operation range for the standard and (A) grade products is 1.8 V ≤ V
≤ V
to the reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input a
low level to the RESET pin.
With the standard and (A) grade products, if the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MIN.)
on power application, input a low level to the RESET pin after power application and before the voltage
reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using an option byte (POCMODE = 1).
With the (A2) grade products, if the voltage rises to 2.7 V at a rate slower than 0.75 V/ms (MIN.) on power
application, input a low level to the RESET pin after power application and before the voltage reaches 2.7 V.
The oscillation accuracy stabilization time of the internal high-speed oscillation clock is included in the
internal voltage stabilization time.
The CPU clock can be switched from the internal high-speed oscillation clock to the high-speed system
clock or to the subsystem clock
oscillation stabilization time. To use the XT1 clock
of the stabilization time.
The 78K0/KB2 is not provided with subsystem clock and XT1 clock.
LVI
POC
LVI
DD
Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
)
: LVI detection voltage
stops
: POC detection voltage
DD
≤ 5.5 V for the (A2) grade products. To set the voltage range below the guaranteed operation range
specified by software.
Wait for voltage
Starting oscillation is
(1.93 to 5.39 ms)
0.5 V/ms (MIN.)
Note 4
stabilization
Reset processing (11 to 45 s)
Note 2, 3
used for reset
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
and Low-Voltage Detector (1/2)
Note 6
Note 5
Reset period
(oscillation
. To use the X1 clock, use the OSTC register to confirm the lapse of the
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
used for interrupt
Reset processing (11 to 45 s)
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
Note 6
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
Note 5
, use the timer function for confirmation of the lapse
Reset period
(oscillation
stop)
(1.93 to 5.39 ms)
Note 4
Wait for voltage
specified by software.
Starting oscillation is
stabilization
Reset processing (11 to 45 s)
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
DD
≤ 5.5 V, and 2.7 V
Note 5
Operation stops
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