UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 261

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already
Caution
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Status Transition
(B) → (C) (X1 clock: 1 MHz ≤ f
(B) → (C) (external main clock: 1 MHz ≤ f
10 MHz)
(B) → (C) (X1 clock: 10 MHz < f
(B) → (C) (external main clock: 10 MHz < f
20 MHz)
(B) → (D) (XT1 clock)
(B) → (D) (external subsystem clock)
Status Transition
Remarks 1. (A) to (I) in Table 6-6 correspond to (A) to (I) in Figure 6-17 and 6-18.
Note The 78K0/KB2 is not provided with a subsystem clock.
been set.
Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 33 ELECTRICAL
SPECIFICATIONS ((A2) GRADE PRODUCTS: T
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
Setting Flag of SFR Register
Setting Flag of SFR Register
Table 6-6. CPU Clock Transition and SFR Register Setting Examples (2/5)
XH
XH
≤ 10 MHz)
≤ 20 MHz)
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don’t care
XH
XH
≤
≤
AMPH
Unnecessary if these registers
XTSTART
0
0
1
1
0
1
0
Note
are already set
Unnecessary if the CPU is operating
EXCLK
A
0
1
0
1
with the subsystem clock
= −40 to +125°C)).
EXCLKS
0
×
1
OSCSEL
1
1
1
1
OSCSELS
MSTOP
with the high-speed
Unnecessary if the
CHAPTER 6 CLOCK GENERATOR
CPU is operating
0
0
0
0
system clock
1
×
1
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Unnecessary
Stabilization
Waiting for
Oscillation
Necessary
XSEL
Note
1
1
1
1
Note
CSS
MCM0
1
1
1
1
1
1
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