UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 376

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
9.4.2 Operation as PWM output
during timer operation is prohibited.
during timer operation is possible.
Hn and the CMP0n register match after the timer count is started. PWM output (TOHn output) outputs an inactive level
when 8-bit timer counter Hn and the CMP1n register match.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
TMHMDn
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register
The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register
The operation in PWM output mode is as follows.
PWM output (TOHn output) outputs an active level and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter
<1> Set each register.
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When
<4> When the 8-bit timer counter Hn and the CMP1n register match, an inactive level is output and the compare
Setting
(i) Setting timer H mode register n (TMHMDn)
(ii) Setting CMP0n register
(iii) Setting CMP1n register
the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is cleared, an
interrupt request signal (INTTMHn) is generated, and an active level is output. At the same time, the compare
register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n
register.
register to be compared with the 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n
register. At this time, the 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
TMHEn
• Compare value (N): Cycle setting
• Compare value (M): Duty setting
Remarks 1. n = 0, 1
0
CKSn2
0/1
2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
CKSn1
Figure 9-11. Register Setting in PWM Output Mode
0/1
CKSn0
0/1
TMMDn1
1
TMMDn0 TOLEVn
0
CHAPTER 9 8-BIT TIMERS H0 AND H1
0/1
TOENn
1
Timer output enabled
Default setting of timer output level
PWM output mode selection
Count clock (f
Count operation stopped
CNT
) selection
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