UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 965

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Serial
interface
IIC0
Multiplier/
divider
Function
If other I
communications are
already in progress
Transfer clock
frequency setting
STT0, SPT0:
Bits 1, 0 of IIC control
register 0 (IICC0)
Transmission reserve When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt
SDR0: Remainder
data register 0
MDA0H, MDA0L:
Multiplication/
division data register
A0
MDB0: Multiplication/
division data register
B0
DMUC0:
Multiplier/divider
control register 0
Details of Function
2
C
−
If I
progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I
recognizes that the SDA0 pin has gone low (detects a start condition). If the value
on the bus at this time can be recognized as an extension code, ACK is returned,
but this interferes with other I
following sequence.
• Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request
• Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I
• Wait for detection of the start condition.
• Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after
Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0
of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 = 1). To
change the transfer clock frequency, clear IICE0 to 0 once.
Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before
they are cleared to 0 is prohibited.
request is generated when the stop condition is detected. Transfer is started when
communication data is written to IIC0 after the interrupt request is generated.
Unless the interrupt is generated when the stop condition is detected, the device
stops in the wait state because the interrupt request is not generated when
communication is started. However, it is not necessary to set SPIE0 to 1 when
MSTS0 (bit 7 of IICS0) is detected by software.
Do not use serial interface IIC0 and the multiplier/divider simultaneously, because
various flags corresponding to interrupt request sources are shared among serial
interface IIC0 and the multiplier/divider.
The value read from SDR0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
SDR0 is reset when the operation is started (when DMUE is set to 1).
MDA0H is cleared to 0 when an operation is started in the multiplication mode
(when multiplier/divider control register 0 (DMUC0) is set to 81H).
Do not change the value of MDA0 during operation processing (while bit 7 (DMUE)
of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the
operation is executed, but the result is undefined.
The value read from MDA0 during operation processing (while DMUE is 1) is not
guaranteed.
Do not change the value of MDB0 during operation processing (while bit 7 (DMUE)
of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the
operation is executed, but the result is undefined.
Do not clear MDB0 to 0000H in the division mode. If set, undefined operation
results are stored in MDA0 and SDR0.
If DMUE is cleared to 0 during operation processing (when DMUE is 1), the
operation result is not guaranteed. If the operation is completed while the clearing
instruction is being executed, the operation result is guaranteed, provided that the
interrupt flag is set.
Do not change the value of DMUSEL0 during operation processing (while DMUE is
1). If it is changed, undefined operation results are stored in multiplication/division
data register A0 (MDA0) and remainder data register 0 (SDR0).
If DMUE is cleared to 0 during operation processing (while DMUE is 1), the
operation processing is stopped. To execute the operation again, set
multiplication/division data register A0 (MDA0), multiplication/division data register
B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the
operation (by setting DMUE to 1).
signal (INTIIC0) when the stop condition is detected.
setting IICE0 to 1), to forcibly disable detection.
2
C operation is enabled and the device participates in communication already in
2
C communications. To avoid this, start I
Cautions
APPENDIX D LIST OF CAUTIONS
2
C.
2
C in the
2
C
p. 584
p. 584
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p. 585
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