UPD78F0500AMC-CAB-AX Renesas Electronics America, UPD78F0500AMC-CAB-AX Datasheet - Page 579

• Manufacturer Part Number: UPD78F0500AMC-CAB-AX
• Description: MCU 8BIT 30SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0500AMC-CAB-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5.12 Arbitration
communication among the master devices is performed as the number of clocks are adjusted until the data differs. This
kind of operation is called arbitration.
(1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high impedance,
which releases the bus.
condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set to 1),
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0) is set
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop
For details of interrupt request timing, see 18.5.17 Timing of I
Remark
Transfer lines
Master 1
Master 2
SDA0
SDA0
SDA0
SCL0
SCL0
SCL0
STD0: Bit 1 of IIC status register 0 (IICS0)
STT0: Bit 1 of IIC control register 0 (IICC0)
Figure 18-19. Arbitration Timing Example
2
C interrupt request (INTIIC0) occurrence.
CHAPTER 18 SERIAL INTERFACE IIC0
Master 1 loses arbitration
Hi-Z
Hi-Z
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