LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet
LE3100MICH S L8YC
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... Dual-Core Intel® Xeon® Processor 3100 Series Datasheet February 2009 Document Number: 319004-002 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Xeon, Pentium, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. * Other names and brands may be claimed as the property of others. ...
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Contents Introduction ....................................................................................................... 9 1 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Terminology Definitions ............................................................ 10 1.2 References ....................................................................................................... 11 Electrical Specifications 2 2.1 Power and Ground Lands.................................................................................... 13 2.2 Decoupling Guidelines ........................................................................................ 13 2.2.1 Vcc Decoupling ...................................................................................... 13 2.2.2 Vtt ...
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... State, and Stop Grant Snoop State90 6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................90 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State.......90 6.2.5 Enhanced Intel SpeedStep 6.2.6 Processor Power Status Indicator (PSI) Signal ............................................91 7 Boxed Processor Specifications 7.1 Introduction ......................................................................................................93 7 ...
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Processor Thermal Profile (65 W) ............................................................................... 80 5-2 Processor Thermal Profile (45 W) ............................................................................... 80 5-3 Case Temperature (TC) Measurement Location ............................................................ 81 5-4 Thermal Monitor 2 Frequency and Voltage Ordering ...................................................... 83 5-5 Conceptual Fan Control Diagram on ...
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Tables 1-1 References ..............................................................................................................11 2-1 Voltage Identification Definition .................................................................................15 2-2 Absolute Maximum and Minimum Ratings ....................................................................17 2-3 Voltage and Current Specifications..............................................................................18 2-4 Processor V Static and Transient Tolerance ...............................................................19 CC 2-5 V Overshoot Specifications......................................................................................20 CC 2-6 FSB Signal Groups ....................................................................................................22 ...
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... Revision History Document Version Revision Number Number 319004 1.0 -001 -002 Datasheet Description • Initial release ® ® • Added Dual-Core Intel Xeon Processor L3110 • Added PSI# signal • Updated VID information Revision Date January 2008 February 2009 7 ...
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Datasheet ...
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... The Dual-Core Intel® Xeon® Processor 3100 Series is a 64- bit processor that maintain compatibility with IA-32 software. In this document, the Dual-Core Intel® Xeon® Processor 3100 Series may be referred to simply as “the processor.” The processors utilize Flip-Chip Land Grid Array (FC-LGA8) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket ...
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... Processor core — Processor die with integrated L2 cache. • LGA775 socket — The Dual-Core Intel® Xeon® Processor 3100 Series mate with the system board through a surface mount, 775-land, LGA socket. • Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package ...
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... Trusted Execution Technology (Intel safer computing initiative which defines a set of hardware enhancements that interoperate with an Intel TXT enabled OS to help protect against software-based attacks. Intel TXT creates a hardware foundation that builds on Intel's Virtualization Technology (Intel VT) to help protect the confidentiality and integrity of data stored/created on the client PC. • ...
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Introduction Datasheet ...
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Electrical Specifications 2 Electrical Specifications 2.1 Power and Ground Lands The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V connected to a system ground plane. The processor ...
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... VID Range values provided in Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Extended HALT State). The processor uses selection of power supply voltages. Table 2-1 specifies the voltage level corresponding to the state of VID[7:0]. A ‘ ...
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Electrical Specifications Table 2-1. Voltage Identification Definition VID VID VID VID VID VID VID ...
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Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands any other signal (including each other) can result in component malfunction TT, or incompatibility with future processors. See Chapter ...
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Electrical Specifications 2.5 Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the processor will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors ...
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... VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep 2. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data ...
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Electrical Specifications Table 2-4. Processor V Static and Transient Tolerance Notes: 1. The loadline specification includes both static and transient ...
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Figure 2-1. Processor V Static and Transient Tolerance VID - 0.000 VID - 0.013 VID - 0.025 VID - 0.038 VID - 0.050 VID - 0.063 VID - 0.075 VID - 0.088 VID - 0.100 VID - ...
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Electrical Specifications Figure 2-2. V Overshoot Example Waveform CC VID + 0.050 VID - 0.000 0 Notes measured overshoot voltage measured time duration above VID. OS 2.6.4 Die Voltage Validation Overshoot events on ...
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... Clock BCLK[1:0], ITP_CLK[1:0] VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, 2 DBR# , VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0] Electrical Specifications . Intel chipsets will also TT 1 Signals 3 , DBSY#, DRDY#, HIT#, Associated Strobe 3 ADSTB0# ADSTB1# DSTBP0#, DSTBN0# ...
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Electrical Specifications 1. Refer to Section 4 processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the ...
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... TT 2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature ...
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Electrical Specifications die to external management devices for thermal/fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI) Specification. Table 2-12. PECI DC Electrical Limits Symbol Definition and Conditions V Input Voltage Range in ...
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... The processor supports Half Ratios between 7.5 and 13.5, refer to The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Table 2-14. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB ...
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Electrical Specifications 2.8.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 2-15 frequency associated with each combination. The required frequency is determined by the processor, chipset, and ...
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Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage. 5. Measurement taken from differential waveform. Table 2-17. ...
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Electrical Specifications Figure 2-4. Measurement Points for Differential Clock Waveforms +150 mV 0.0V -150 mV Diff Datasheet Slew_rise V_swing T5 = BCLK[1:0] rise and fall time through the swing region § § Slew _fall +150mV 0.0V -150mV 29 ...
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Electrical Specifications Datasheet ...
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Package Mechanical Specifications 3 Package Mechanical Specifications 3.1 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted ...
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Reference datums 6. All drawing dimensions are in mm [in]. 7. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal/Mechanical Design Guidelines. 32 Package Mechanical ...
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Package Mechanical Specifications Figure 3-2. Processor Package Drawing Sheet Datasheet 33 ...
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Figure 3-3. Processor Package Drawing Sheet Package Mechanical Specifications Datasheet ...
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Package Mechanical Specifications Figure 3-4. Processor Package Drawing Sheet 3.1.2 Processor Component Keep-Out Zones Datasheet 35 ...
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The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side ...
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... The coordinates are referred to throughout the document to identify processor lands. Datasheet Material Nickel Plated Copper Fiber Reinforced Resin Gold Plated Copper INTEL ©'06 3110 M INTEL® XEON® SLxxx [COO] 3.00GHZ/6M/1333/06 [FPO ATPO S/N 37 ...
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Figure 3-6. Processor Land Coordinates and Quadrants, Top View ...
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Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in ...
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Figure 4-1. land-out Diagram (Top View – Left Side VCC VCC VSS VSS AM VCC VCC VSS VSS AL VCC VCC VSS VSS AK VSS VSS VSS VSS AJ VSS VSS VSS VSS AH VCC ...
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Land Listing and Signal Descriptions Figure 4-2. land-out Diagram (Top View – Right Side VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC VSS VCC VCC VSS VCC ...
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Table 4-1. Alphabetical Land Assignments Land Name Land # A10# A11# A12# A13# A14# A15# A16# A17# AB6 A18# A19# A20# A20M# A21# AA4 A22# AD6 A23# AA5 A24# AB5 A25# AC5 A26# AB4 A27# A28# A29# AG6 A3# A30# ...
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Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # BSEL1 H30 BSEL2 G30 COMP0 A13 COMP1 COMP2 COMP3 COMP8 B13 D0# D1# D10# B10 D11# C11 D12# D13# B12 D14# C12 D15# D11 D16# D17# ...
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Table 4-1. Alphabetical Land Assignments Land Name Land # D46# D22 D47# G22 D48# D20 D49# D17 D5# D50# D51# C15 D52# C14 D53# D54# C18 D55# D56# D57# D58# C21 D59# D6# D60# D61# D62# D63# B22 D7# D8# ...
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Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # FC24 AK1 FC25 AL1 FC26 E29 FC27 FC28 FC29 FC3 FC30 FC31 J16 FC32 H15 FC33 H16 FC34 J17 FC35 FC36 AD3 FC37 AB3 FC38 G10 ...
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Table 4-1. Alphabetical Land Assignments Land Name Land # RESERVED D14 RESERVED D16 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET# G23 RS0# RS1# RS2# SKTOCC# AE8 SMI# STPCLK# TCK AE1 TDI AD1 TDO TESTHI0 TESTHI1 TESTHI10 TESTHI11 ...
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Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # VCC AD28 VCC AD29 VCC AD30 VCC AD8 VCC AE11 VCC AE12 VCC AE14 VCC AE15 VCC AE18 VCC AE19 VCC AE21 VCC AE22 VCC AE23 ...
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Table 4-1. Alphabetical Land Assignments Land Name Land # VCC AH25 VCC AH26 VCC AH27 VCC AH28 VCC AH29 VCC AH30 VCC AH8 VCC AH9 VCC AJ11 VCC AJ12 VCC AJ14 VCC AJ15 VCC AJ18 VCC AJ19 VCC AJ21 VCC ...
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Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # VCC AM14 VCC AM15 VCC AM18 VCC AM19 VCC AM21 VCC AM22 VCC AM25 VCC AM26 VCC AM29 VCC AM30 VCC AM8 VCC AM9 VCC AN11 ...
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Table 4-1. Alphabetical Land Assignments Land Name Land # VCC K24 VCC K25 VCC K26 VCC K27 VCC K28 VCC K29 VCC K30 VCC VCC VCC M23 VCC M24 VCC M25 VCC M26 VCC M27 VCC M28 VCC M29 VCC ...
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Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # VCC W23 VCC W24 VCC W25 VCC W26 VCC W27 VCC W28 VCC W29 VCC W30 VCC W8 VCC Y23 VCC Y24 VCC Y25 VCC Y26 ...
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Table 4-1. Alphabetical Land Assignments Land Name Land # VSS AA23 VSS AA24 VSS AA25 VSS AA26 VSS AA27 VSS AA28 VSS AA29 VSS AA3 VSS AA30 VSS AA6 VSS AA7 VSS AB1 VSS AB23 VSS AB24 VSS AB25 VSS ...
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Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # VSS AF25 VSS AF26 VSS AF27 VSS AF28 VSS AF29 VSS AF3 VSS AF30 VSS AF6 VSS AF7 VSS AG10 VSS AG13 VSS AG16 VSS AG17 ...
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Table 4-1. Alphabetical Land Assignments Land Name Land # VSS AK24 VSS AK27 VSS AK28 VSS AK29 VSS AK30 VSS AK5 VSS AK7 VSS AL10 VSS AL13 VSS AL16 VSS AL17 VSS AL20 VSS AL23 VSS AL24 VSS AL27 VSS ...
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Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # VSS D15 VSS D18 VSS D21 VSS D24 VSS VSS VSS VSS VSS E11 VSS E14 VSS E17 VSS VSS E20 VSS E25 VSS E26 VSS ...
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Table 4-1. Alphabetical Land Assignments Land Name Land # VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 56 Table 4-1. Signal Buffer Direction Land ...
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Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Land # VSS V26 VSS V27 VSS V28 VSS V29 VSS VSS V30 VSS VSS VSS W4 VSS W7 VSS VSS VSS VSS_MB_ AN6 REGULATION VSS_SENSE AN4 VSSA ...
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Table 4-2. Numerical Land Assignment Land Land # Name A10 D08# A11 D09# A12 VSS A13 COMP0 A14 D50# A15 VSS A16 DSTBN3# A17 D56# A18 VSS A19 D61# A2 VSS A20 RESERVED A21 VSS A22 D62# A23 VCCA A24 ...
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Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land Land # Name AC27 VCC AC28 VCC AC29 VCC AC3 VSS AC30 VCC AC4 RESERVED AC5 A25# AC6 VSS AC7 VSS AC8 VCC AD1 TDI AD2 BPM2# AD23 VCC ...
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Table 4-2. Numerical Land Assignment Land Land # Name AF28 VSS AF29 VSS AF3 VSS AF30 VSS AF4 A28# AF5 A27# AF6 VSS AF7 VSS AF8 VCC AF9 VCC AG1 TRST# AG10 VSS AG11 VCC AG12 VCC AG13 VSS AG14 ...
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Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land Land # Name AJ12 VCC AJ13 VSS AJ14 VCC AJ15 VCC AJ16 VSS AJ17 VSS AJ18 VCC AJ19 VCC AJ2 BPM0# AJ20 VSS AJ21 VCC AJ22 VCC AJ23 VSS ...
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Table 4-2. Numerical Land Assignment Land Land # Name AL26 VCC AL27 VSS AL28 VSS AL29 VCC AL3 VRDSEL AL30 VCC AL4 VID5 AL5 VID1 AL6 VID3 AL7 VSS AL8 VCC AL9 VCC AM1 VSS AM10 VSS AM11 VCC AM12 ...
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Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land Land # Name AN8 VCC AN9 VCC B1 VSS B10 D10# B11 VSS B12 D13# B13 COMP8 B14 VSS B15 D53# B16 D55# B17 VSS B18 D57# B19 D60# ...
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Table 4-2. Numerical Land Assignment Land Land # Name C9 FC41 D1 RESERVED D10 D22# D11 D15# D12 VSS D13 D25# D14 RESERVED D15 VSS D16 RESERVED D17 D49# D18 VSS D19 DBI2# D2 ADS# D20 D48# D21 VSS D22 ...
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Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land Land # Name F14 D28# F15 D30# F16 VSS F17 D37# F18 D38# F19 VSS F2 FC5 F20 D41# F21 D43# F22 VSS F23 RESERVED F24 TESTHI7 F25 TESTHI2 ...
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Table 4-2. Numerical Land Assignment Land Land # Name H14 VSS H15 FC32 H16 FC33 H17 VSS H18 VSS H19 VSS H2 GTLREF1 H20 VSS H21 VSS H22 VSS H23 VSS H24 VSS H25 VSS H26 VSS H27 VSS H28 ...
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Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land Land # Name L23 VSS L24 VSS L25 VSS L26 VSS L27 VSS L28 VSS L29 VSS L3 VSS L30 VSS L4 A06# L5 A03# L6 VSS L7 VSS ...
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Table 4-2. Numerical Land Assignment Land Land # Name R30 VSS R4 A08# R5 VSS R6 ADSTB0# R7 VSS R8 VCC T1 COMP1 T2 FC4 T23 VCC T24 VCC T25 VCC T26 VCC T27 VCC T28 VCC T29 VCC T3 ...
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Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land Land # Name Y1 FC0/ BOOTSELE CT Y2 VSS Y23 VCC Y24 VCC Y25 VCC Y26 VCC Y27 VCC Y28 VCC Y29 VCC Y3 FC17 Datasheet Table 4-2. Signal ...
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Alphabetical Signals Reference Table 4-3. Signal Description (Sheet Name A[35:3]# A20M# ADS# ADSTB[1:0]# BCLK[1:0] BNR# BPM[5:0]# 70 Type 36 Input/ A[35:3]# (Address) define a 2 Output sub-phase 1 of the address phase, these signals transmit the ...
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Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet Name BPRI# BR0# BSEL[2:0] COMP[3:0], COMP8 D[63:0]# DBI[3:0]# Datasheet Type Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must ...
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Table 4-3. Signal Description (Sheet Name DBR# DBSY# DEFER# DPRSTP# DPSLP# DRDY# DSTBN[3:0]# 72 Type Output DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is ...
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... Normal state. For additional information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. Input GTLREF[1:0] determine the signal reference level for GTL+ input signals ...
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... Output On a processor these signals are connected on the package to Vss alternative to MSID, Intel has implemented the Power Segment Identifier (PSID) to report the maximum Thermal Design Power of the processor. Refer to the Platform Design Guide for additional information regarding PSID. ...
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Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet Name REQ[4:0]# RESET# RESERVED RS[2:0]# SKTOCC# SMI# STPCLK# TCK TDI TDO TESTHI[13:0] Datasheet Type Input/ REQ[4:0]# (Request Command) must connect the appropriate pins/lands of Output all processor ...
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Table 4-3. Signal Description (Sheet Name THERMTRIP# TMS TRDY# TRST# VCC VCCA VCCIOPLL VCCPLL VCC_SENSE VCC_MB_ REGULATION VID[7:0] VID_SELECT VRDSEL VSS 76 Type Output In the event of a catastrophic cooling failure, the processor will automatically shut ...
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Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet Name VSSA VSS_SENSE VSS_MB_ REGULATION VTT VTT_OUT_LEFT VTT_OUT_RIGHT VTT_SEL Datasheet Type Input VSSA provides isolated ground for internal PLLs on previous generation processors. It may be left ...
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Land Listing and Signal Descriptions Datasheet ...
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... In order to determine a processor's case temperature specification based on the thermal profile necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the Wolfdale Processors Thermal and Mechanical Design Guidelines Addendum and the Live Die System Thermal Testing Basics for the details of this methodology ...
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... The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption ...
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Thermal Specifications and Design Considerations Table 5-2. Processor Thermal Profile (65 W) Maximum Tc Power (W) (°C) 0 45.1 2 45.9 4 46.8 6 47.6 8 48.5 10 49.3 12 50.1 14 51.0 16 51.8 18 52.7 20 53.5 22 ...
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Figure 5-1. Processor Thermal Profile (65 W) 72.0 68.0 64.0 60.0 56.0 52.0 48.0 44.0 0 Figure 5-2. Processor Thermal Profile ( ...
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... Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. Datasheet ) for the processor is specified in C illustrates where Intel recommends T ) Measurement Location C Measure T Measure T (geometric center of the package) (geometric center of the package) 37 ...
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With a properly designed and characterized thermal solution anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods ...
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Thermal Specifications and Design Considerations voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to ensure proper operation once the processor reaches its normal operating frequency. Refer to Figure 5-4. ...
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... Platform Environment Control Interface (PECI) 5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices ...
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Thermal Specifications and Design Considerations wide range (2Kbps to 2Mbps). The PECI interface on the processor is disabled by default and must be enabled through BIOS. More information can be found in the Platform Environment Control Interface (PECI) Specification. 5.3.1.1 ...
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PECI Fault Handling Requirements PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and ...
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Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to The sampled information configures ...
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... LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT powerdown state. See the Intel Architecture Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more information. ...
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Features The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT powerdown state, the processor will ...
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... In order to support this technology, the system must support dynamic VID transitions. Switching between voltage/frequency states is software controlled. Enhanced Intel SpeedStep Technology is a technology that creates processor performance states (P states). P states are power consumption and capability states within the Normal state as shown in enables real-time dynamic switching between frequency and voltage points ...
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... In order to run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep Technology: • Voltage/Frequency selection is software controlled by writing to processor MSR's (Model Specific Registers), thus eliminating chipset dependency. ...
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Features Datasheet ...
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... Boxed Processor Specifications 7.1 Introduction The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor ...
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Mechanical Specifications 7.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. mechanical representation of the boxed processor. Clearance is required around ...
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Boxed Processor Specifications Figure 7-3. Top View Space Requirements for the Boxed Processor Notes: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 7-4. Overall View Space Requirements ...
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Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink ...
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Boxed Processor Specifications Table 7-1. Fan Heatsink Power and Signal Specifications Description +12V: 12 volt fan power supply IC: - Maximum fan steady-state current draw - Average fan steady-state current draw - Maximum fan start-up current draw - Fan start-up ...
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Table 5-1) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly critical that ...
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Boxed Processor Specifications Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) 7.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The ...
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... As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage. The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by more accurate measurement of processor die temperature through the processor's Digital Thermal Sensors (DTS) and PECI ...
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Boxed Processor Specifications If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard CPU fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor ...
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Boxed Processor Specifications Datasheet ...
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... Due to the complexity of Dual-Core Intel® Xeon® Processor 3100 Series systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a Dual-Core Intel® Xeon® Processor 3100 Series system that can make use of an LAI: mechanical and electrical. ...
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Debug Tools Specifications Datasheet ...