LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 93

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Features
6.2.6
Datasheet
best serve the performance and power requirements of the processor and system. Note
that the front side bus is not altered; only the internal core frequency is changed. In
order to run at reduced power consumption, the voltage is altered in step with the bus
ratio.
The following are key features of Enhanced Intel SpeedStep Technology:
Processor Power Status Indicator (PSI) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a
reduced power consumption state. PSI# can be used to improve efficiency of the
voltage regulator, resulting in platform power savings. For details, refer to the
compatible chipset Platform Design Guide and Voltage Regulator-Down (VRD) 11.1
Processor Power Delivery Design Guidelines.
PSI# may be asserted only when the processor is in the Deeper Sleep state.
• Voltage/Frequency selection is software controlled by writing to processor MSR's
(Model Specific Registers), thus eliminating chipset dependency.
- If the target frequency is higher than the current frequency, Vcc is incremented in
steps (+12.5 mV) by placing a new value on the VID signals after which the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
- If the target frequency is lower than the current frequency, the processor shifts to
the new frequency and Vcc is then decremented in steps (-12.5 mV) by changing
the target VID through the VID signals.
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