LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 76

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 4-3.
76
Signal Description (Sheet 7 of 8)
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VCCA
VCCIOPLL
VCCPLL
VCC_SENSE
VCC_MB_
REGULATION
VID[7:0]
VID_SELECT
VRDSEL
VSS
Name
Output
Output
Output
Output
Output
Input
Input
Input
Input
Type
Input
Input
Input
Input
Input
In the event of a catastrophic cooling failure, the processor will automatically
shut down when the silicon has reached a temperature approximately 20 °C
above the maximum T
the processor junction temperature has reached a level beyond where
permanent silicon damage may occur. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To protect the
processor, its core voltage (V
THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 µs of
the assertion of PWRGOOD (provided V
disabled on de-assertion of PWRGOOD (if V
THERMTRIP# may also be disabled). Once activated, THERMTRIP# remains
latched until PWRGOOD, V
the PWRGOOD, V
processor’s junction temperature remains at or above the trip level,
THERMTRIP# will again be asserted within 10 µs of the assertion of
PWRGOOD (provided V
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to
receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven low during power on Reset. Refer to the eXtended Debug Port: Debug
Port Design Guide for UP and DP Platforms for complete implementation
details.
VCC are the power pins for the processor. The voltage supplied to these pins
is determined by the VID[7:0] pins.
VCCA provides isolated power for internal PLLs on previous generation
processors. It may be left as a No-Connect on boards supporting the Wolfdale
processor.
previous generation processors. It may be left as a No-Connect on boards
supporting the Wolfdale processor.
VCC_SENSE is an isolated low impedance connection to processor core power
(V
noise.
This land is provided as a voltage regulator feedback sense point for V
connected internally in the processor package to the sense point land U27 as
described in the Voltage Regulator-Down (VRD) 11.0 Processor Power
Delivery Design Guidelines For Desktop LGA775 Socket.
power supply voltages (V
or the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket for more information. The voltage
supply for these signals must be valid before the VR can supply V
processor. Conversely, the VR output must be disabled until the voltage
supply for the VID signals becomes valid. The VID signals are needed to
support the processor voltage specification variations. See
definitions of these signals. The VR must supply the voltage that is requested
by the signals, or disable itself.
This land is tied high on the processor package and is used by the VR to
choose the proper VID table. Refer to the appropriate platform design guide
or the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design
Guidelines For Desktop LGA775 Socket for more information.
This input should be left as a no connect in order for the processor to boot.
The processor will not boot on legacy platforms where this land is connected
to V
VSS are the ground pins for the processor and should be connected to the
system ground plane.
VCCIOPLL provides isolated power for internal processor FSB PLLs on
VCCPLL provides isolated power for internal processor FSB PLLs.
The VID (Voltage ID) signals are used to support automatic selection of
CC
SS
). It can be used to sense or measure voltage near the silicon with little
.
TT
or V
C
TT
. Assertion of THERMTRIP# (Thermal Trip) indicates
CC
CC
and V
TT
signal will de-assert THERMTRIP#, if the
). Refer to the appropriate platform design guide
or V
CC
) must be removed following the assertion of
CC
Description
CC
are valid).
is de-asserted. While the de-assertion of
Land Listing and Signal Descriptions
TT
and V
TT
or V
CC
CC
are asserted) and is
are not valid,
Table 2-1
CC
Datasheet
to the
for
CC
. It is