LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 70

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4.2
Table 4-3.
70
Alphabetical Signals Reference
Signal Description (Sheet 1 of 8)
A[35:3]#
A20M#
ADS#
ADSTB[1:0]#
BCLK[1:0]
BNR#
BPM[5:0]#
Name
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Input
Type
Input
A[35:3]# (Address) define a 2
sub-phase 1 of the address phase, these signals transmit the address of a
transaction. In sub-phase 2, these signals transmit transaction type
information. These signals must connect the appropriate pins/lands of all
agents on the processor FSB. A[35:3]# are source synchronous signals and
are latched into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples a
subset of the A[35:3]# signals to determine power-on configuration. See
Section 6.1
address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor's address wrap-around at the 1-MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this
signal following an Input/Output write instruction, it must be valid along with
the TRDY# assertion of the corresponding Input/Output Write bus
transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the
ADS# activation to begin protocol checking, address decode, internal snoop,
or deferred reply ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising
and falling edges. Strobes are associated with signals as shown below.
The differential pair BCLK (Bus Clock) determines the FSB frequency. All
processor FSB agents must receive these signals to drive their outputs and
latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing V
BNR# (Block Next Request) is used to assert a bus stall by any bus agent
unable to accept new bus transactions. During a bus stall, the current bus
owner cannot issue any new transactions.
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins/lands of all
processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY#
is a processor output used by debug tools to determine processor debug
readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port.
PREQ# is used by debug tools to request debug operation of the processor.
Refer to the appropriate platform design guide for more detailed information.
These signals do not have on-die termination. Refer to
appropriate platform design guide for termination requirements.
If A20M# (Address-20 Mask) is asserted, the processor masks physical
for more details.
CROSS
REQ[4:0]#, A[16:3]#
A[35:17]#
.
Signals
36
Description
-byte physical memory address space. In
Land Listing and Signal Descriptions
ADSTB1#
ADSTB0#
Associated Strobe
Section
2.7.2, and
Datasheet