LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 23

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications
.
Table 2-7.
Table 2-8.
2.7.2
2.7.3
Table 2-9.
Datasheet
1.
2.
3.
4.
Signal Characteristics
Notes:
1.
Signal Reference Voltages
Note:
1.
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/
deasserted for at least eight BCLKs in order for the processor to recognize the proper
signal state. See
timing requirements for entering and leaving the low power states.
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
GTL+ Signal Group DC Specifications
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#,
PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY#
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#,
TDO, FCx
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY#
Symbol
V
V
V
I
Refer to
In processor systems where no debug port is implemented on the system board, these signals are used to
support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration
options. See
PROCHOT# signal type is open drain output and CMOS input.
Signals that do not have R
See
OL
OH
IH
IL
Table 2-10
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
Section 4.2
Open Drain Signals
Section 6.1
Parameter
Signals with R
for more information.
Section 2.7.3
for signal descriptions.
GTLREF
for details.
TT
, nor are actively driven to their high-voltage level.
TT
1
and DC specifications. See
GTLREF + 0.10
V
TT
-0.10
Min
N/A
- 0.10
A20M#, BCLK[1:0], BPM[5:0]#, BSEL[2:0],
COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#,
INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/NMI,
MSID[1:0], PWRGOOD, RESET#, SMI#, STPCLK#,
TDO, TESTHI[13:0], THERMTRIP#, VID[7:0],
GTLREF[1:0], TCK, TDI, TMS, TRST#, VTT_SEL
[(R
A20M#, LINT0/INTR, LINT1/NMI, IGNNE#,
INIT#, PROCHOT#, PWRGOOD
STPCLK#, TCK
TT_MIN
GTLREF - 0.10
V
V
) + (2 * R
TT
TT_MAX
Max
V
Signals with No R
+ 0.10
Section 6.2
TT
1
/
, TDI
ON_MIN
V
1
TT
, TMS
)]
/2
for additional
1
, TRST#
Unit
TT
1
V
V
V
A
, SMI#,
1
Notes
3, 4, 6
2, 6
4, 6
-
1
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