LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 72

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 4-3.
72
Signal Description (Sheet 3 of 8)
DBR#
DBSY#
DEFER#
DPRSTP#
DPSLP#
DRDY#
DSTBN[3:0]#
Name
Output
Output
Output
Output
Input/
Input
Input
Input/
Input/
Input
Type
DBR# (Debug Reset) is used only in processor systems where no debug port
is implemented on the system board. DBR# is used by a debug port
interposer so that an in-target probe can drive system reset. If a debug port
is implemented in the system, DBR# is a no connect in the system. DBR# is
not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data
on the processor FSB to indicate that the data bus is in use. The data bus is
released after DBSY# is de-asserted. This signal must connect the
appropriate pins/lands on all processor FSB agents.
DEFER# is asserted by an agent to indicate that a transaction cannot be
ensured in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or input/output agent. This signal
must connect the appropriate pins/lands of all processor FSB agents.
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. To
return to the Deep Sleep State, DPRSTP# must be deasserted. Use
of the DPRSTP# pin, and corresponding low power state, requires
chipset support and may not be available on all platforms. Refer to
the appropriate platform design guide for implementation details.
NOTE: Some processors may not have the Deeper Sleep State
DPSLP#, when asserted on the platform, causes the processor to
transition from the Sleep State to the Deep Sleep state. To return
to the Sleep State, DPSLP# must be deasserted. Use of the
DPSLP# pin, and corresponding low power state, requires chipset
support and may not be available on all platforms. Refer to the
appropriate platform design guide for implementation details.
NOTE: Some processors may not have the Deep Sleep State
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be de-asserted to insert idle clocks. This signal must connect the
appropriate pins/lands of all processor FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
enabled, refer to the Specification Update for specific sku
and stepping guidance.
enabled, refer to the Specification Update for specific sku
and stepping guidance.
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Signals
Description
Land Listing and Signal Descriptions
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
Associated Strobe
Datasheet