LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 22

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

2.7.1
Table 2-6.
22
provided on the processor silicon and are terminated to V
provide on-die termination, thus eliminating the need to terminate the bus on the
motherboard for most GTL+ signals.
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[1:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle.
and asynchronous.
FSB Signal Groups
Notes:
GTL+ Common
Clock Input
GTL+ Common
Clock I/O
GTL+ Source
Synchronous I/O
GTL+ Strobes
CMOS
Open Drain Output
Open Drain Input/
Output
FSB Clock
Power/Other
Signal Group
Table 2-6
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
Synchronous to
assoc. strobe
Synchronous to
BCLK[1:0]
Clock
identifies which signals are common clock, source synchronous,
Type
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
ADS#, BNR#, BPM[5:0]#, BR0#
HITM#, LOCK#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#,
NMI, SMI#
TRST#, BSEL[2:0],
FERR#/PBE#, IERR#, THERMTRIP#, TDO
PROCHOT#
BCLK[1:0], ITP_CLK[1:0]
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0],
COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION,
DBR#
MSID[1:0]
REQ[4:0]#, A[16:3]#
A[35:17]#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
2
, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI,
DPRSTP#. DPSLP#,
Signals
3
4
, STPCLK#, PWRGOOD,
3
VID[7:0], PSI#
3
2
TT
Signals
IGNNE#, INIT#, LINT0/INTR, LINT1/
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
. Intel chipsets will also
Associated Strobe
3
, DBSY#, DRDY#, HIT#,
SLP#,
1
Electrical Specifications
TCK, TDI, TMS,
Datasheet