LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 16

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

2.4
16
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to V
V
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.
In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see
termination.
Unused active high inputs, should be connected through a resistor to ground (V
Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (R
TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs
must be terminated on the motherboard. Unused outputs may be terminated on the
motherboard or left unconnected. Note that leaving unused outputs unterminated may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing.
All TESTHI[13:0] lands should be individually connected to V
which matches the nominal trace impedance.
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
Terminating multiple TESTHI pins together with a single pull-up resistor is not
recommended for designs supporting boundary scan for proper Boundary Scan testing
of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for
TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of
the board transmission line traces. For example, if the nominal trace impedance is 50
Ω
TT,
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals
• TESTHI13 – cannot be grouped with other TESTHI signals
, then a value between 40 Ω and 60 Ω should be used.
or to any other signal (including each other) can result in component malfunction
Table 2-6
for details on GTL+ signals that do not include on-die
TT
). For details see
TT
via a pull-up resistor
Electrical Specifications
Table
2-13.
CC
Datasheet
SS
, V
).
SS
,