LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 25

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications
Table 2-12. PECI DC Electrical Limits
.
2.7.3.2
Table 2-13. GTL+ Bus Voltage Definitions
Datasheet
die to external management devices for thermal/fan speed control. More detailed
information may be found in the Platform Environment Control Interface (PECI)
Specification.
1. V
2. The leakage specification applies to powered devices on the PECI bus.
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths might appear
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See
termination. Refer to the appropriate platform design guidelines for specific
implementation details.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF.
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits. For more details on platform design, see the
applicable platform design guide.
Notes:
1.
Notes:
GTLREF_PU
GTLREF_PD
R
COMP[3:0]
COMP8
V
Symbol
TT
hysteresis
I
I
V
Table 2-3
as additional nodes.
I
source
I
C
leak+
Symbol
leak-
TT
noise
V
V
V
sink
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
bus
in
n
p
supplies the PECI interface. PECI behavior does not affect V
for V
Input Voltage Range
Hysteresis
Negative-edge threshold voltage
Positive-edge threshold voltage
High level output source
(V
Low level output sink
(V
High impedance state leakage to V
High impedance leakage to GND
Bus capacitance per node
Signal noise immunity above 300 MHz
OH
OL
GTLREF pull up
GTLREF pull down
Termination Resistance
COMP Resistance
COMP Resistance
TT
= 0.25 * V
= 0.75 * V
specifications.
Definition and Conditions
Table 2-7
Parameter
TT
TT)
)
resistor
resistor
for details on which GTL+ signals do not include on-die
Table 2-13
TT
57.6 * 0.99
100 * 0.99
lists the GTLREF specifications. The GTL+
49.40
24.65
Min
45
0.1 * V
0.1 * V
0.275 *
0.550 *
-0.15
-6.0
N/A
N/A
N/A
Min
V
V
0.5
TT
TT
TT
TT
TT
49.90
24.90
57.6
Typ
100
min/max specifications. Please refer to
50
0.500 *
0.725 *
Max
N/A
V
V
V
1.0
50
10
10
-
-
TT
TT
TT
57.6 * 1.01
100 * 1.01
50.40
25.15
Max
55
Units
V
mA
mA
µA
µA
pF
V
V
V
V
p-p
Units
Ω
Ω
Ω
Ω
Ω
Notes
2
2
3
4
4
Notes
3
4
2
3
1
25
1