LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 75

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Land Listing and Signal Descriptions
Table 4-3.
Datasheet
Signal Description (Sheet 6 of 8)
REQ[4:0]#
RESET#
RESERVED
RS[2:0]#
SKTOCC#
SMI#
STPCLK#
TCK
TDI
TDO
TESTHI[13:0]
Name
Output
Output
Output
Input/
Type
Input
Input
Input
Input
Input
Input
Input
REQ[4:0]# (Request Command) must connect the appropriate pins/lands of
all processor FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB0#.
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For
a power-on Reset, RESET# must stay active for at least one millisecond after
V
RESET#, all FSB agents will de-assert their outputs within two clocks.
RESET# must not be kept asserted for more than 10 ms while PWRGOOD is
asserted.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are
described in the
This signal does not have on-die termination and must be terminated on the
system board.
All RESERVED lands must remain unconnected. Connection of these lands to
V
component malfunction or incompatibility with future processors.
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins/lands of all processor FSB agents.
SKTOCC# (Socket Occupied) will be pulled to ground by the processor.
System board designers may use this signal to determine if the processor is
present.
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, the processor saves the
current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor will tri-
state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core
units except the FSB and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK#
is de-asserted, the processor restarts its internal clock to all units and
resumes execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides
the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TESTHI[13:0] must be connected to the processor’s appropriate power
source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description)
through a resistor for proper processor operation. See
details.
CC
CC
, V
and BCLK have reached their proper specifications. On observing active
SS
, V
TT
, or to any other signal (including each other) can result in
Section
6.1.
Description
Section 2.4
for more
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