LE3100MICH S L8YC Intel, LE3100MICH S L8YC Datasheet - Page 28

• Manufacturer Part Number: LE3100MICH S L8YC
• Manufacturer: Intel

Specifications of LE3100MICH S L8YC

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 2-17. FSB Differential Clock Specifications (1333 MHz FSB)
Figure 2-3.
28
3.
4.
5.
Notes:
1.
2.
3.
4.
5.
6.
Differential Clock Waveform
BCLK[1:0] Frequency
T1: BCLK[1:0] Period
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew Rate
Slew Rate Matching
“Steady state” voltage, not including overshoot or undershoot.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute
value of the minimum voltage.
Measurement taken from differential waveform.
Unless otherwise noted, all specifications in this table apply to all processor core frequencies based on a
333 MHz BCLK[1:0].
The period specified here is the average period. A given period may vary from this specification as
governed by the period stability specification (T2). Min period specification is based on -300 PPM deviation
from a 3 ns period. Max period specification is based on the summation of +300 PPM deviation from a 3 ns
period and a +0.5% maximum variance due to spread spectrum clocking.
In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
Slew rate is measured through the VSWING voltage range centered about differential zero. Measurement
taken from differential waveform.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a
±75mV window centered on the average cross point where Clock rising meets Clock# falling. The median
cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate
calculations.
Duty Cycle (High time/Period) must be between 40 and 60%
Threshold
Region
T# Parameter
Tp = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
BCLK0
BCLK1
V
CROSS (ABS
Tph
331.633
2.99970
)
Min
N/A
2.5
Tp
-
V
CROSS (ABS
Tpl
Nom
N/A
-
-
-
-
)
333.367
3.01538
Max
150
20
8
Ringback
Margin
Unit
V/ns
MHz
ns
ps
%
Electrical Specifications
Overshoot
Undershoot
VH
Rising Edge
VL
Falling Edge
Ringback
Ringback
Figure
2-3
2-3
2-4
-
Datasheet
7
2
3
4
5
Notes
1